W7100A WIZnet, W7100A Datasheet - Page 89

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

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PLL_CLK) time.
an interrupt occurs, the related bit in IR2 is enabled. In this case, the INT5 (nINT5: TCPIPcore
interrupt) signal is asserted low until all of the bits of IR2 is ‘0’. Once the IR2 register is
cleared out by using the Sn_IR bits, the INT5 signal is asserted high.
Bit
a. At the socket 0, assume an interrupt occurs (S0_IR(3) = ‘1’) and corresponding IR2 bit is
b. Also assume an interrupt continually occurs (S1_IR(0) = ‘1’) on the socket1 and
c. When the Host clears S0_IR(S0_IR = 0x00), the corresponding IR2 bit is also cleared
d. When the S1_IR is cleared, but the corresponding IR2 is not 0x00 because of socket1
However, as INTLEVEL is 0x000F, the internal INT5 signal is asserted after the I
IR2 (W7100A SOCKET Interrupt Register)[R/W][0xFE0034][0x00]
IR2 is a Register which notifies the host that a W7100A SOCKET interrupt has occurred. When
S7_INT
7
6
7
set as ‘1’ (IR(S0_IR) = ‘1’). Then the internal INT5 signal is asserted low.
corresponding IR bit set as ‘1’ (IR(S1_IR) = ‘1’).
(IR(S0_IR) = ‘0’). Internal INT5 signal will be de-asserted high(deactivated) from
low(activaed).
interrupt, internal INT5 signal should be asserted low.
Symbol
S7_INT
S6_INT
S6_INT
6
Occurrence of SOCKET 7 Interrupt
When an interrupt occurs at SOCKET 7, it becomes ‘1’. This interrupt
information is applied to S7_IR. This bit is automatically cleared when
S7_IR is cleared to 0x00 by host.
Occurrence of SOCKET 6 Interrupt
When an interrupt occurs at SOCKET 6, it becomes ‘1’. This interrupt
S5_INT
5
S4_INT
4
S3_INT
3
Description
S2_INT
2
S1_INT
Ver. 1.12
1
S0_INT
0
AWT
(16
89