W7100A WIZnet, W7100A Datasheet - Page 90

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

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Bit
8.3.2 SOCKET Registers
7
Sn_MR (SOCKET n Mode Register)[R/W][0xFE4000 + 0x100n][0x0000]
This register configures the protocol type or option of SOCKET n.
5
4
3
2
1
0
MULTI
7
Symbol
MULTI
S5_INT
S4_INT
S3_INT
S2_INT
S1_INT
S0_INT
6
Multicasting
0 : disable Multicasting
1 : enable Multicasting
information is applied to S6_IR. This bit is automatically cleared when
S6_IR is cleared to 0x00 by host.
Occurrence of SOCKET 5 Interrupt
When an interrupt occurs at SOCKET 5, it becomes ‘1’. This interrupt
information is applied to S5_IR. This bit is automatically cleared when
S5_IR is cleared to 0x00 by host.
Occurrence of SOCKET 4 Interrupt
When an interrupt occurs at SOCKET 4, it becomes ‘1’. This interrupt
information is applied to S4_IR. This bit is automatically cleared when
S4_IR is cleared to 0x00 by host.
Occurrence of SOCKET 3 Interrupt
When an interrupt occurs at SOCKET 3, it becomes ‘1’. This interrupt
information is applied to S3_IR. This bit is automatically cleared when
S3_IR is cleared to 0x00 by host.
Occurrence of SOCKET 2 Interrupt
When an interrupt occurs at SOCKET 2, it becomes ‘1’. This interrupt
information is applied to S2_IR. This bit is automatically cleared when
S2_IR is cleared to 0x00 by host.
Occurrence of SOCKET 1 Interrupt
When an interrupt occurs at SOCKET 1, it becomes ‘1’. This interrupt
information is applied to S1_IR. This bit is automatically cleared when
S1_IR is cleared to 0x00 by host.
Occurrence of SOCKET 0 Interrupt
When an interrupt occurs at SOCKET 0, it becomes ‘0’. This interrupt
information is applied to S0_IR. This bit is automatically cleared when
S0_IR is cleared to 0x00 by host.
ND / MC
5
4
Description
P3
3
P2
2
Ver. 1.12
P1
1
P0
0
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