MK40DN512VMD10 Freescale Semiconductor, MK40DN512VMD10 Datasheet

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MK40DN512VMD10

Manufacturer Part Number
MK40DN512VMD10
Description
ARM Microcontrollers - MCU KINETIS 512K USB LCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK40DN512VMD10

Rohs
yes
Core
ARM Cortex M4
Processor Series
K40
Data Bus Width
32 bit
Maximum Clock Frequency
100 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
MAPBGA-144
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK40DN512VMD10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MK40DN512VMD10
Quantity:
111
Freescale Semiconductor
Data Sheet: Technical Data
K40 Sub-Family
Supports the following:
MK40DX128VLQ10,
MK40DX128VMD10,
MK40DX256VLQ10,
MK40DX256VMD10,
MK40DN512VLQ10,
MK40DN512VMD10
Features
• Operating Characteristics
• Performance
• Memories and memory interfaces
• Clocks
• System peripherals
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012 Freescale Semiconductor, Inc.
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
– Up to 100 MHz ARM Cortex-M4 core with DSP
– Up to 512 KB program flash memory on non-
– Up to 256 KB program flash memory on
– Up to 256 KB FlexNVM on FlexMemory devices
– 4 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
– Multiple low-power modes to provide power
– Memory protection unit with multi-master
– 16-channel DMA controller, supporting up to 63
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
instructions delivering 1.25 Dhrystone MIPS per
MHz
FlexMemory devices
FlexMemory devices
optimization based on application requirements
protection
request sources
• Security and integrity modules
• Human-machine interface
• Analog modules
• Timers
K40P144M100SF2V2
– Hardware CRC module to support fast cyclic
– 128-bit unique identification (ID) number per chip
– Segment LCD controller supporting up to 40
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
– Two 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
– Two 12-bit DACs
– Two transimpedance amplifiers
– Three analog comparators (CMP) containing a 6-bit
– Voltage reference
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
– Two 2-channel quadrature decoder/general purpose
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
Document Number: K40P144M100SF2V2
redundancy checks
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes, depending on the package size
integrated into each ADC
DAC and programmable reference input
timer
timers
Rev. 2, 12/2012

Related parts for MK40DN512VMD10

MK40DN512VMD10 Summary of contents

Page 1

... K40 Sub-Family Supports the following: MK40DX128VLQ10, MK40DX128VMD10, MK40DX256VLQ10, MK40DX256VMD10, MK40DN512VLQ10, MK40DN512VMD10 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1 ...

Page 2

... USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – I2S module K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 2 Freescale Semiconductor, Inc. ...

Page 3

... Capacitance attributes........................................20 5.3 Switching specifications.....................................................20 5.3.1 Device clock specifications.................................20 5.3.2 General switching specifications.........................21 5.4 Thermal specifications.......................................................22 5.4.1 Thermal operating requirements.........................22 K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Table of Contents 5.4.2 Thermal attributes...............................................22 6 Peripheral operating requirements and behaviors....................23 6.1 Core modules....................................................................23 6.1.1 Debug trace timing specifications.......................23 6.1.2 JTAG electricals..................................................24 6 ...

Page 4

... Pinout........................................................................................72 8.1 K40 Signal Multiplexing and Pin Assignments..................72 K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 4 8.2 K40 Pinouts.......................................................................78 9 Revision History........................................................................80 Freescale Semiconductor, Inc. ...

Page 5

... Qualification status K## Kinetis family A Key attribute M Flash memory type K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. www.freescale.com and perform a part number search for Description • Fully qualified, general market flow • Prequalification • K40 • Cortex-M4 w/ DSP • Cortex-M4 w/ DSP and FPU • ...

Page 6

... LQ = 144 LQFP ( mm) • 144 MAPBGA ( mm) • 256 MAPBGA ( mm) • MHz • MHz • 100 MHz • 120 MHz • 150 MHz • Tape and reel • (Blank) = Trays Values Freescale Semiconductor, Inc. ...

Page 7

... An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. Max. 0.9 1.1 Min. Max. 10 130 Min. ...

Page 8

... V core supply DD voltage 3.5 Result of exceeding a rating Measured characteristic K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 8 Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Max. Unit V Freescale Semiconductor, Inc. ...

Page 9

... Typical values are provided as design guidelines and are neither tested nor guaranteed. K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Normal operating range Degraded operating range - No permanent failure - No permanent failure ...

Page 10

... Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply voltage DD K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 10 Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Max. Unit 130 µ 150 °C 105 °C 25 °C –40 °C Unit °C V Freescale Semiconductor, Inc. ...

Page 11

... Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol Description V Digital supply voltage DD K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. –55 — Min. — Min. -2000 -500 -100 Table continues on the next page ...

Page 12

... Nonswitching electrical specifications K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 12 Min. Max. Unit — 185 mA –0.3 5.5 V –0 0 – – –0.3 3.63 V –0.3 3.63 V –0.3 6.0 V –0.3 3.8 V Freescale Semiconductor, Inc. ...

Page 13

... If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(V calculated as R=(V -V )/|I |. Select the larger of these two calculated resistances. IN AIO_MAX IC K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. 1.71 1.71 –0.1 –0.1 1.71 0.7 × V 0.75 × V — ...

Page 14

... K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 14 supply LVD and POR operating requirements Min. 0.8 2.48 2.62 2.72 2.82 2.92 — 1.54 1.74 1.84 1.94 2.04 — 0.97 900 Min. 0.8 Typ. Max. Unit Notes 1.1 1.5 V 2.56 2.64 V 2.70 2.78 V 2.80 2.88 V 2.90 2.98 V 3.00 3.08 V ±80 — mV 1.60 1.66 V 1.80 1.86 V 1.90 1.96 V 2.00 2.06 V 2.10 2.16 V ±60 — mV 1.00 1.03 V 1000 1100 μs Typ. Max. Unit Notes 1.1 1.5 V Freescale Semiconductor, Inc ...

Page 15

... All specifications except t POR assume this clock configuration: • CPU and system clocks = 100 MHz • Bus clock = 50 MHz • FlexBus clock = 50 MHz • Flash clock = 25 MHz K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. = -9mA V – 0 -3mA V – ...

Page 16

... Table continues on the next page... Max. Unit Notes 300 μs 1 112 μs 74 μs 73 μs 5.9 μs 5.8 μs 5 μs Max. Unit Notes See note — — — — Freescale Semiconductor, Inc. ...

Page 17

... I Average current with RTC and 32kHz disabled at DD_VBAT 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. Typ. — 0.77 — 0.74 — 2.45 — 6.61 — ...

Page 18

... Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 18 Min. Typ. Max. Unit — 0.57 0.67 μA — 0.90 1.2 μA — 2.4 3.5 μA — 0.67 0.94 μA — 1.0 1.4 μA — 2.7 3.9 μA Freescale Semiconductor, Inc. Notes 10 ...

Page 19

... ° MHz (crystal OSC K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Frequency Typ. band (MHz) 0.15–50 23 50–150 27 150–500 28 500– ...

Page 20

... VLPR mode — — — — — Table continues on the next page... Min. Max. Unit — — Max. Unit Notes 100 MHz — MHz 50 MHz 50 MHz 25 MHz 25 MHz 4 MHz 4 MHz 4 MHz 0.5 MHz 16 MHz Freescale Semiconductor, Inc. ...

Page 21

... Port rise and fall time (low drive strength) • Slew disabled • 1.71 ≤ V ≤ 2.7V DD • 2.7 ≤ V ≤ 3.6V DD • Slew enabled • 1.71 ≤ V ≤ 2.7V DD • 2.7 ≤ V ≤ 3.6V DD K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. Max. Unit — 25 MHz — 16 MHz — 8 MHz — 12.5 MHz — ...

Page 22

... K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 22 144 LQFP 144 MAPBGA Table continues on the next page... Min. Max. Unit –40 125 °C –40 105 °C Unit Notes °C/W 1 °C/W 1 °C/W 1 °C/W 1 Freescale Semiconductor, Inc. ...

Page 23

... T Clock and data rise time r T Clock and data fall time f T Data setup s T Data hold h K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 144 LQFP 144 Unit MAPBGA 24 16 °C °C ° ...

Page 24

... K40 Sub-Family Data Sheet, Rev. 2, 12/2012 Table continues on the next page... Ts Th Min. Max. Unit 2.7 3.6 V MHz 1/J1 — — — — ns — — — ns — — — — ns — — Freescale Semiconductor, Inc. ...

Page 25

... J12 TCLK low to TDO high-Z J13 TRST assert time J14 TRST setup time (negation) to TCLK high TCLK (input) K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 5. Test clock input timing Min. Max. ...

Page 26

... TDO TDO K40 Sub-Family Data Sheet, Rev. 2, 12/2012 J11 J12 J11 Figure 7. Test Access Port timing J5 J6 Input data valid Output data valid Output data valid J9 J10 Input data valid Output data valid Output data valid Freescale Semiconductor, Inc. ...

Page 27

... Loss of external clock minimum frequency — loc_low RANGE = 00 f Loss of external clock minimum frequency — loc_high RANGE = 01, 10 K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J14 Figure 8. TRST timing Table 15. MCG specifications Min. Typ. — ...

Page 28

... MHz 4, — MHz — MHz — MHz ps 180 — 150 — — — 100 MHz — µA 600 — µA — 4.0 MHz 120 — — ps — ps 600 — ps — ± 2.98 % — ± 5.97 % Freescale Semiconductor, Inc ...

Page 29

... Supply current — low-power mode (HGO=0) DDOSC • 32 kHz • 4 MHz • 8 MHz (RANGE=01) • 16 MHz • 24 MHz • 32 MHz K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — — Min. Typ. 1.71 — ...

Page 30

... MΩ — MΩ — — MΩ 1 — MΩ — — kΩ 200 — kΩ — — kΩ 0 — kΩ 0.6 — — 0.6 — — Freescale Semiconductor, Inc ...

Page 31

... This section describes the module electrical characteristics. 6.3.3.1 32 kHz oscillator DC electrical specifications Table 18. 32kHz oscillator DC electrical specifications Symbol Description V Supply voltage BAT R Internal feedback resistor F K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 32 — 3 — 8 — — — ...

Page 32

... Min. — — — Min. Typ. Max. — — 0.6 — Typ. Max. Unit Notes 32.768 — kHz 1000 — ms 32.768 — kHz — BAT Typ. Max. Unit Notes 7.5 18 μs 13 113 ms 104 904 ms Freescale Semiconductor, Inc. Unit ...

Page 33

... KB EEPROM backup setram64k t • 256 KB EEPROM backup setram256k t Byte-write to erased FlexRAM location execution eewr8bers time K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — — — — — — — ...

Page 34

... Typ. Max. Unit 2.5 6.0 mA 1.5 4.0 mA Freescale Semiconductor, Inc. ...

Page 35

... EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 Min. ...

Page 36

... Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • n — data flash cycling endurance (the following graph assumes 10,000 nvmcycd cycles) K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 36 EEESPLIT × EEESIZE × Write_efficiency × n nvmcycd Freescale Semiconductor, Inc. ...

Page 37

... EZP_CK high to EZP_D input invalid (hold) EP7 EZP_CK low to EZP_Q output valid EP8 EZP_CK low to EZP_Q output invalid (hold) EP9 EZP_CS negation to EZP_Q tri-state K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. 1.71 3.6 — f ...

Page 38

... Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 38 EP3 EP2 EP4 EP9 EP8 EP7 EP5 EP6 Figure 10. EzPort Timing Diagram Min. 2.7 — 20 — 0.5 8.5 0.5 Max. Unit Notes 3.6 V FB_CLK MHz — — — — Freescale Semiconductor, Inc. ...

Page 39

... Data and FB_TA input hold 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. Unit 1 ...

Page 40

... Peripheral operating requirements and behaviors FB1 FB_CLK FB_A[Y] FB2 FB_D[X] Address FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 11. FlexBus read timing diagram K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 40 FB3 FB5 Address FB4 Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ Freescale Semiconductor, Inc. ...

Page 41

... FB_TA FB_TSIZ[1:0] Figure 12. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB3 Address Data AA=1 AA=0 FB4 ...

Page 42

... Table 29 and 1 Max. Unit Notes — 3 +100 +100 DDA DDA V V SSA SSA — 31/ VREFH — VREFH kΩ 3 — 5 kΩ — 18.0 MHz 4 — 12.0 MHz 4 5 — 818.330 Ksps Freescale Semiconductor, Inc. ...

Page 43

... ADC electrical characteristics Table 28. 16-bit ADC characteristics (V Symbol Description Conditions I Supply current DDA_ADC K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 37.037 — = 1.0 MHz unless otherwise stated. Typical values are for ADCK ADC calculator tool ...

Page 44

... Notes 3 MHz ADACK f ADACK 6.1 MHz 7.3 MHz 9.5 MHz 4 ±6.8 LSB 5 ±2.1 4 -1.1 to +1.9 LSB 5 -0.3 to 0.5 4 -2.7 to +1.9 LSB 5 -0.7 to +0.5 4 -5.4 LSB V = ADIN V DDA -1 — LSB ±0.5 6 — bits — bits — bits — bits dB 7 — dB — — dB — dB Freescale Semiconductor, Inc. ...

Page 45

... Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = ...

Page 46

... VREF_OU VREF_OU VREF_OU — SSA V — SSA — 128 — 64 — 32 — 100 1.25 — Table continues on the next page... Max. Unit Notes 3 DDA V V DDA 4 — kΩ IN+ to IN- — — — Ω 5 — µs 6 Freescale Semiconductor, Inc. ...

Page 47

... I Input DC current DC_PGA Gain = =0.5V CM Gain =64 =0.1V CM K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 Min. Typ. 18.484 — 37.037 — MHz unless otherwise stated. Typical values are for ADCK PGAD Min. ...

Page 48

... V from 1.71 DDA to 3.6V 0.31 %/ leakage AS In current (refer to the MCU's voltage and current operating ratings × 0.583 — dB 16-bit differential — dB mode, Average=32 — dB 16-bit differential — dB mode, Average=32, f =100Hz in Freescale Semiconductor, Inc. ...

Page 49

... Supply voltage DD I Supply current, High-speed mode (EN=1, PMODE=1) DDHS I Supply current, low-speed mode (EN=1, PMODE=0) DDLS V Analog input voltage AIN V Analog input offset voltage AIO K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 85 105 53 88 11.6 13.4 8.0 13.6 7.2 9.6 6.3 9 ...

Page 50

... K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 50 Min. 1 — — — — V – 0.5 DD — — — –0.5 –0.3 -0.6V. DD Typ. Max. Unit 5 — — — — mV — — V — 0 200 ns 250 600 ns — 40 μs 7 — μA 3 — 0.5 LSB — 0.3 LSB Freescale Semiconductor, Inc. ...

Page 51

... Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1.3 1.6 1.9 2.2 Vin level (V) HYSTCTR S etting 2.5 2.8 3.1 51 ...

Page 52

... A small load capacitance (47 pF) can improve the bandwidth performance of the DAC K40 Sub-Family Data Sheet, Rev. 2, 12/2012 1.3 1.6 1.9 2.2 Vin level (V) Min. 1.71 1.13 Operating temperature range of the device — — or the voltage output of the VREF module (VREF_OUT) DDA HYSTCTR Setting 2.5 2.8 3.1 Max. Unit Notes 3 °C 100 Freescale Semiconductor, Inc. ...

Page 53

... Calculated by a best fit curve from V 6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set to 0x800, Temp range from -40C to 105C K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. ...

Page 54

... Peripheral operating requirements and behaviors Figure 18. Typical INL error vs. digital code K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 54 Freescale Semiconductor, Inc. ...

Page 55

... VREF_OUT if the VREF_OUT functionality is being used for either an internal or external L reference. 2. The load capacitance should not exceed +/-25% of the nominal specified C the device. K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. Unit 1.71 3 ...

Page 56

... Min. Max. Unit 0 50 °C Min. Max. Unit 1.173 1.225 V Freescale Semiconductor, Inc. Unit Notes µ µ µ Notes Notes ...

Page 57

... Standby mode V Regulator output voltage — Input supply Reg33out (VREGIN) < 3.6 V, pass-through mode C External output capacitor OUT ESR External output capacitor equivalent series resistance K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 0.5 0 14.25 0.25 Min. Typ. 2.7 — ...

Page 58

... Max. Unit — 290 — mA Min. Max. Unit 2.7 3.6 V — 25 MHz — ns BUS (t /2) − / SCK SCK ( − — ns BUS − — ns BUS 2 — — — — ns Freescale Semiconductor, Inc. Notes . Load Notes 1 2 ...

Page 59

... DSPI_SS inactive to DSPI_SOUT not driven DSPI_SS DSPI_SCK (CPOL=0) DSPI_SOUT DS13 DSPI_SIN Figure 21. DSPI classic SPI timing — slave mode K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DS1 DS2 DS8 Data Last data First data DS5 ...

Page 60

... Last data First data DS5 DS6 First data Data Last data Description Table continues on the next page... Max. Unit Notes 3 12.5 MHz — SCK/2) — — 8.5 ns — ns — ns — ns DS4 Min. Max. Unit 1.71 3.6 V — 6.25 MHz Freescale Semiconductor, Inc. ...

Page 61

... Figure 23. DSPI classic SPI timing — slave mode 2 6.8 switching specifications See General switching specifications. 6.8.8 UART switching specifications See General switching specifications. K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Description DS10 DS15 DS12 First data Data DS14 First data Data Min. ...

Page 62

... K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 62 Card input clock SD3 SD2 SD1 SD6 SD7 SD8 Figure 24. SDHC timing Min. Max. Unit 0 400 kHz 0 25 MHz 0 20 MHz 0 400 kHz 7 — — ns — — 6 — — ns Freescale Semiconductor, Inc. ...

Page 63

... I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid S8 I2S_TX_BCLK to I2S_TXD invalid S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. 2.7 3 — ns 45% 55% ...

Page 64

... Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K40 Sub-Family Data Sheet, Rev. 2, 12/2012 S10 Min. 2.7 80 45% 4.5 2 — — — S6 S10 S8 Max. Unit 3.6 V — ns 55% MCLK period — ns — — ns — ns — Freescale Semiconductor, Inc. ...

Page 65

... I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid S8 I2S_TX_BCLK to I2S_TXD invalid S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S11 S12 S15 S16 S18 Min. 1.71 40 45% ...

Page 66

... Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K40 Sub-Family Data Sheet, Rev. 2, 12/2012 S10 Min. 1.71 80 45% 5.8 2 — — — S6 S10 S8 Max. Unit 3.6 V — ns 55% MCLK period — ns — 20.6 — ns — ns — Freescale Semiconductor, Inc. ...

Page 67

... I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid S8 I2S_TX_BCLK to I2S_TXD invalid S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S11 S12 S15 S16 S18 Min. 1.71 62.5 45% ...

Page 68

... Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K40 Sub-Family Data Sheet, Rev. 2, 12/2012 S10 Min. 1.71 250 45 — — S6 S10 S8 Max. Unit 3.6 V — ns 55% MCLK period — ns — — ns — ns — Freescale Semiconductor, Inc. ...

Page 69

... MaxSens Maximum sensitivity Res Resolution T Response time @ 20 pF Con20 I Current added in run mode TSI_RUN I Low power mode current adder TSI_LP K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S11 S12 S15 S16 S18 Min. Typ. 1.71 — — ...

Page 70

... Table continues on the next page... * PS * NSCN) = 1.0 pF ref = 0.5 pF ref Max. Unit Notes 58 Hz — — 8000 — V — V — V — V — V — IREG Freescale Semiconductor, Inc. ...

Page 71

... Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing the drawing’s document number: If you want the drawing for this package 144-pin LQFP 144-pin MAPBGA K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Min. Typ. — 1 — 10 — ...

Page 72

... I2S0_TXD1 UART5_RX I2S0_RX_ BCLK PTE10 UART5_CTS_ I2S0_TXD0 b PTE11 UART5_RTS_ I2S0_TX_FS b ALT5 ALT6 ALT7 EzPort FB_AD27 I2C1_SDA RTC_CLKOUT FB_AD26 I2C1_SCL SPI1_SIN FB_AD24 SPI1_SOUT FB_CS3_b/ FB_TA_b FB_BE7_0_b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_b FB_ALE/ USB_SOF_ FB_CS1_b/ OUT FB_TS_b FB_CS0_b FB_AD4 FB_AD3 FB_AD2 FB_AD1 Freescale Semiconductor, Inc. ...

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... CMP1_IN3/ CMP1_IN3/ CMP1_IN3/ ADC0_SE23 ADC0_SE23 ADC0_SE23 39 L4 DAC1_OUT/ DAC1_OUT/ DAC1_OUT/ CMP0_IN4/ CMP0_IN4/ CMP0_IN4/ CMP2_IN3/ CMP2_IN3/ CMP2_IN3/ ADC1_SE23 ADC1_SE23 ADC1_SE23 K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTE12 I2S0_TX_ BCLK Pinout ALT5 ALT6 ALT7 EzPort FB_AD0 73 ...

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... SWD_DIO NMI_b EZP_CS_b CMP2_OUT I2S0_TX_ JTAG_TRST_ BCLK b CLKOUT TRACE_ CLKOUT FB_AD18 TRACE_D3 FB_AD17 FTM1_QD_ TRACE_D2 PHA FB_AD16 FTM1_QD_ TRACE_D1 PHB FB_AD15 FTM2_QD_ TRACE_D0 PHA FB_OE_b FTM2_QD_ PHB FB_CS5_b/ I2S0_TXD0 FTM1_QD_ FB_TSIZ1/ PHA FB_BE23_16_ b FB_CS4_b/ I2S0_TX_FS FTM1_QD_ FB_TSIZ0/ PHB Freescale Semiconductor, Inc. ...

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... LCD_P5/ LCD_P5/ ADC1_SE11 ADC1_SE11 87 F12 PTB6 LCD_P6/ LCD_P6/ ADC1_SE12 ADC1_SE12 88 F11 PTB7 LCD_P7/ LCD_P7/ ADC1_SE13 ADC1_SE13 K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTA14 SPI0_PCS0 UART0_TX PTA15 SPI0_SCK UART0_RX PTA16 SPI0_SOUT UART0_CTS_ b/ UART0_COL_ b PTA17 SPI0_SIN ...

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... LCD_P9 FTM0_FLT1 LCD_P10 FTM0_FLT2 LCD_P11 EWM_IN LCD_P12 EWM_OUT_b LCD_P13 FTM2_QD_ LCD_P14 PHA FTM2_QD_ LCD_P15 PHB CMP0_OUT LCD_P16 CMP1_OUT LCD_P17 CMP2_OUT LCD_P18 LCD_P19 I2S0_TXD1 LCD_P20 I2S0_TXD0 LCD_P21 I2S0_TX_FS LCD_P22 CLKOUT I2S0_TX_ LCD_P23 BCLK CMP1_OUT LCD_P24 CMP0_OUT LCD_P25 I2S0_MCLK LCD_P26 Freescale Semiconductor, Inc. ...

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... F8 VDD VDD VDD 138 A1 PTD7 LCD_P47 LCD_P47 139 B3 PTD10 DISABLED 140 B2 PTD11 DISABLED K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTC7 SPI0_SIN USB_SOF_ I2S0_RX_FS OUT PTC8 I2S0_MCLK PTC9 I2S0_RX_ BCLK PTC10 I2C1_SCL I2S0_RX_FS PTC11/ ...

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... Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K40 Sub-Family Data Sheet, Rev. 2, 12/2012. 78 ALT1 ALT2 ALT3 ALT4 PTD12 SPI2_SCK SDHC0_D4 PTD13 SPI2_SOUT SDHC0_D5 PTD14 SPI2_SIN SDHC0_D6 PTD15 SPI2_PCS1 SDHC0_D7 ALT5 ALT6 ALT7 EzPort FB_AD7 FB_AD6 FB_AD5 FB_RW_b Freescale Semiconductor, Inc. ...

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... PGA1_DP/ADC1_DP0/ADC0_DP3 29 PGA1_DM/ADC1_DM0/ADC0_DM3 30 VDDA 31 VREFH 32 VREFL 33 VSSA 34 ADC1_SE16/CMP2_IN2/ADC0_SE22 35 ADC0_SE16/CMP1_IN2/ADC0_SE21 36 Figure 31. K40 144 LQFP Pinout Diagram K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Pinout 108 VLL3 107 VSS 106 PTC3/LLWU_P7 105 PTC2 104 PTC1/LLWU_P6 103 PTC0 102 PTB23 101 PTB22 PTB21 ...

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... PTB19 PTB18 E PTB17 PTB16 PTB11 PTB10 F PTB9 PTB8 PTB7 PTB6 G PTB5 PTB4 PTB3 PTB2 PTB0/ H PTB1 PTA29 PTA28 LLWU_P5 PTA13/ J PTA27 PTA26 PTA25 LLWU_P4 K PTA12 PTA16 PTA17 PTA24 L PTA11 PTA14 PTA15 RESET_b M PTA10 VSS PTA19 PTA18 Freescale Semiconductor, Inc. ...

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... K40 Sub-Family Data Sheet, Rev. 2, 12/2012. Freescale Semiconductor, Inc. Revision History 81 ...

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... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time ...

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