MK40DN512ZVLL10 Freescale Semiconductor, MK40DN512ZVLL10 Datasheet

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MK40DN512ZVLL10

Manufacturer Part Number
MK40DN512ZVLL10
Description
ARM Microcontrollers - MCU KINETIS 512K USB LCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK40DN512ZVLL10

Rohs
yes
Core
ARM Cortex M4
Processor Series
K40
Data Bus Width
32 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT

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MK40DN512ZVLL10
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Freescale Semiconductor
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MK40DN512ZVLL10
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Freescale Semiconductor
Data Sheet: Technical Data
K40 Sub-Family Data Sheet
Supports the following:
MK40DN512ZVLL10
Features
• Operating Characteristics
• Performance
• Memories and memory interfaces
• Clocks
• System peripherals
• Security and integrity modules
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2011–2013 Freescale Semiconductor, Inc.
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
– Up to 100 MHz ARM Cortex-M4 core with DSP
– Up to 512 KB program flash memory on non-
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
– Multiple low-power modes to provide power
– Memory protection unit with multi-master
– 16-channel DMA controller, supporting up to 63
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
– Hardware CRC module to support fast cyclic
– 128-bit unique identification (ID) number per chip
instructions delivering 1.25 Dhrystone MIPS per
MHz
FlexMemory devices
optimization based on application requirements
protection
request sources
redundancy checks
• Human-machine interface
• Analog modules
• Timers
• Communication interfaces
– Segment LCD controller supporting up to 40
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
– Two 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
– 12-bit DAC
– Three analog comparators (CMP) containing a 6-bit
– Voltage reference
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
– Two 2-channel quadrature decoder/general purpose
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
– USB full-/low-speed On-the-Go controller with on-
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Five UART modules
– Secure Digital host controller (SDHC)
– I2S module
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes, depending on the package size
integrated into each ADC
DAC and programmable reference input
timer
timers
chip transceiver
K40P100M100SF2
Document Number: K40P100M100SF2
Rev. 7, 02/2013

Related parts for MK40DN512ZVLL10

MK40DN512ZVLL10 Summary of contents

Page 1

... Freescale Semiconductor Data Sheet: Technical Data K40 Sub-Family Data Sheet Supports the following: MK40DN512ZVLL10 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1 ...

Page 2

... Inter-Integrated Circuit Interface (I2C) timing..... 53 6.8.8 UART switching specifications............................54 6.8.9 SDHC specifications...........................................54 6.8.10 I2S switching specifications................................55 6.9 Human-machine interfaces (HMI)......................................58 6.9.1 TSI electrical specifications................................58 6.9.2 LCD electrical characteristics.............................59 7 Dimensions...............................................................................60 7.1 Obtaining package dimensions.........................................60 8 Pinout........................................................................................60 8.1 K40 Signal Multiplexing and Pin Assignments..................60 8.2 K40 Pinouts.......................................................................64 Freescale Semiconductor, Inc. ...

Page 3

... Revision History........................................................................65 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 3 ...

Page 4

... Description • Fully qualified, general market flow • Prequalification • K40 • Cortex-M4 w/ DSP • Cortex-M4 w/ DSP and FPU • Program flash only • Program flash and FlexMemory Table continues on the next page... Values Freescale Semiconductor, Inc. ...

Page 5

... An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Description • • • ...

Page 6

... Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 6 Min. Max. 0.9 1.1 Min. Max. 10 130 Min. Max. — 7 Unit V Unit µA Unit pF Freescale Semiconductor, Inc. ...

Page 7

... Result of exceeding a rating Measured characteristic K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Terminology and guidelines Max ...

Page 8

... Normal operating range Degraded operating range - No permanent failure - No permanent failure - Correct operation - Possible decreased life - Possible incorrect operation Operating (power on) Handling range No permanent failure Handling (power off) Fatal range Expected permanent failure ∞ Fatal range Expected permanent failure ∞ Freescale Semiconductor, Inc. ...

Page 9

... Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply voltage DD K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Terminology and guidelines Max ...

Page 10

... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 10 Min. Max. Unit –55 150 °C — 260 °C — 245 Min. Max. Unit — 3 — Min. Max. Unit -2000 +2000 V -500 +500 V -100 +100 mA Freescale Semiconductor, Inc. Notes 1 2 Notes 1 Notes ...

Page 11

... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. General Min. Max. Unit – ...

Page 12

... ESD protection diodes Max. Unit Notes 3.6 V 3.6 V 0.1 V 0.1 V 3.6 V — — 0.35 × 0.3 × — — — +5 — — V — less than V or greater IN AIO_MIN -V )/|I |. Select the IN AIO_MAX ICAIO Freescale Semiconductor, Inc ...

Page 13

... Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description V Falling VBAT supply POR detect voltage POR_VBAT K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. supply LVD and POR operating requirements Min. 0.8 2.48 2.62 2.72 2.82 2.92 — ...

Page 14

... Table continues on the next page... 1 Typ. Max. Unit Notes — — V — — V — — V — — V — 100 mA — 0.5 V — 0.5 V — 0.5 V — 0.5 V — 100 mA 3, 0.5 μA 1.5 μA 10 μA 4, 0.5 μA 0.5 μA 1 μ μ μ μ μA Freescale Semiconductor, Inc ...

Page 15

... POR assume this clock configuration: • CPU and system clocks = 100 MHz • Bus clock = 50 MHz • Flash clock = 25 MHz • MCG mode: FEI K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. — — — — — ...

Page 16

... Table continues on the next page... Max. Unit Notes μs 1 300 1 slew rate) 134 μs 96 μs 96 μs 6.2 μs 5.9 μs 5.9 μs Max. Unit Notes See note — — — Freescale Semiconductor, Inc. ...

Page 17

... I Average current with RTC and 32kHz disabled at DD_VBAT 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. Typ. — N/A — N/A — 0.59 — 2.26 — ...

Page 18

... Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 18 Min. Typ. Max. Unit — 0.71 0.81 μA — 1.01 1.3 μA — 2.82 4.3 μA — 0.84 0.94 μA — 1.17 1.5 μA — 3.16 4.6 μA Freescale Semiconductor, Inc. Notes 10 ...

Page 19

... TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. Freescale Semiconductor, Inc. Frequency band (MHz) 0.15– ...

Page 20

... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013 MHz 48MHz SYS BUS Table 8. Capacitance attributes Min. Normal run mode — 20 — — — Min. Max. Unit — — Max. Unit Notes 100 MHz — MHz 50 MHz 25 MHz 25 MHz Freescale Semiconductor, Inc. ...

Page 21

... This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes load load 5.4 Thermal specifications K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. Max. Unit 1.5 — Bus clock ...

Page 22

... Thermal 20 resistance, junction to board Thermal 9 resistance, junction to case Thermal 2 characterization parameter, junction to package top outside center (natural convection) Min. Max. Unit –40 125 °C –40 105 °C Unit Notes °C/W 1 °C/W 1 °C/W 1 °C/W 1 °C/W 2 °C/W 3 °C/W 4 Freescale Semiconductor, Inc. ...

Page 23

... Clock and data fall time f T Data setup s T Data hold h Figure 3. TRACE_CLKOUT specifications TRACE_CLKOUT TRACE_D[3:0] Figure 4. Trace data specifications K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Frequency dependent 2 2 — — Max ...

Page 24

... Min. Max. Unit 1.71 3.6 V MHz 1/J1 — — — ns 12.5 — ns — Freescale Semiconductor, Inc. ...

Page 25

... TRST setup time (negation) to TCLK high TCLK (input) TCLK Data inputs Data outputs Data outputs Data outputs Figure 6. Boundary scan (JTAG) timing K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 5. Test clock input timing Min ...

Page 26

... There are no specifications necessary for the device's system modules. 6.3 Clock modules K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 26 J11 J12 J11 Figure 7. Test Access Port timing J14 Figure 8. TRST timing J9 J10 Input data valid Output data valid Output data valid Freescale Semiconductor, Inc. ...

Page 27

... MHz VCO • MHz VCO t FLL target frequency acquisition time fll_acquire K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 15. MCG specifications Min. — 32.768 31.25 — ± 0.3 — ± 1.5 — ...

Page 28

... MHz pll_ref 2.0 — — 120 — 50 — 1350 — 600 ± 1.49 — ± 4.47 — — — Max. Unit Notes 100 MHz 7 — µA 7 — µA 4.0 MHz 8 — ps — — ps — ps ± 2.98 % ± 5. 150 × 1075( pll_ref Freescale Semiconductor, Inc. ...

Page 29

... Series resistor — low-frequency, high-gain mode (HGO=1) Series resistor — high-frequency, low-power mode (HGO=0) Series resistor — high-frequency, high-gain mode (HGO=1) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 1.71 — — ...

Page 30

... Typ. Max. Unit Notes 0.6 — — 0.6 — — Typ. Max. Unit Notes — 40 kHz — 8 MHz — 32 MHz — 50 MHz 750 — 250 — ms 0.6 — — ms Freescale Semiconductor, Inc ...

Page 31

... XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and V clock must be within the range of V 6.4 Memories and memory interfaces K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors NOTE Min. — ...

Page 32

... Table continues on the next page... Max. Unit Notes 18 μs 113 ms 1 3616 ms 1 Max. Unit Notes 1 μ μ μs 1 145 μs 2 3700 ms 114 ms 2 — ms — ms — μs 1 — μs 7400 μs 1 Freescale Semiconductor, Inc. ...

Page 33

... EzPort Switching Specifications Table 24. EzPort switching specifications Num Description Operating voltage EP1 EZP_CK frequency of operation (all commands except READ) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 200 — 70 — ...

Page 34

... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 34 EP3 EP2 EP4 EP9 EP8 EP7 EP5 EP6 Figure 9. EzPort Timing Diagram Min. Max. Unit — MHz SYS — ns EZP_CK 5 — — — — ns — — ns — Freescale Semiconductor, Inc. ...

Page 35

... C ADC conversion ≤ 13-bit modes rate rate No ADC hardware averaging Continuous conversions enabled, subsequent conversion time K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 25 and Table 26 Min. Typ. 1. -100 ...

Page 36

... V REFH DDA 1 Min. Typ. 0.215 — Table continues on the next page... 1 Max. Unit Notes 5 461.467 Ksps /C AS tool. SIMPLIFIED CHANNEL SELECT CIRCUIT ADC SAR ENGINE R ADIN R ADIN R ADIN R ADIN C ADIN , REFL SSA 2 Max. Unit Notes 1 Freescale Semiconductor, Inc. AS ...

Page 37

... Avg = 32 SFDR Spurious free 16-bit differential mode dynamic range • Avg = 32 16-bit single-ended mode • Avg = 32 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = REFH DDA REFL 1 Min. Typ. ...

Page 38

... DDA REFL 1 Min. Typ. I × 1.55 1.62 706 716 = V REFH DDA = 2.0 MHz unless otherwise stated. Typical values are for ADCK = V ) (continued) SSA 2 Max. Unit Notes leakage current (refer to the MCU's voltage and current operating ratings) 1.69 mV/°C 726 mV Freescale Semiconductor, Inc. ...

Page 39

... Differential input Gain = PGAD impedance Gain = 16, 32 Gain = 64 R Analog source AS resistance T ADC sampling S time K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 Min. Typ. 1.71 — VREF_OU VREF_OU VREF_OU — SSA V — ...

Page 40

... MHz unless otherwise stated. Typical values are for ADCK PGAD Min. Typ. — 420 =1.2V, — 1.54 REFPGA =1.2V, — 0.57 REFPGA Table continues on the next page... Max. Unit Notes 450 Ksps 7 250 Ksps 8 /2 causes drop AS 1 Max. Unit Notes 644 μ — μA — μA Freescale Semiconductor, Inc. ...

Page 41

... Gain=1 ratio • Gain=64 THD Total harmonic • Gain=1 distortion • Gain=64 SFDR Spurious free • Gain=1 dynamic range • Gain=64 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 0.95 1 1.9 2 3.8 4 7 ...

Page 42

... Typ. Max. Unit — 3.6 V — 200 μA — 20 μA — — — — — — mV — — V — 0 200 ns Freescale Semiconductor, Inc. ...

Page 43

... VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level LSB = V /64 reference 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0.1 0.4 0.7 Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min — — –0.5 –0.3 -0 1.3 1.6 1.9 2.2 Vin level (V) Typ. ...

Page 44

... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013 1.3 1.6 1.9 2.2 Vin level (V) Min. 1.71 1.13 Operating temperature range of the device — — or the voltage output of the VREF module (VREF_OUT) DDA HYSTCTR Setting 2.5 2.8 3.1 Max. Unit Notes 3 °C 100 Freescale Semiconductor, Inc. ...

Page 45

... Calculated by a best fit curve from 3.0 V, reference select set for V DDA 0x800, temperature range is across the full range of the device K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — — ...

Page 46

... Peripheral operating requirements and behaviors Figure 15. Typical INL error vs. digital code K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 46 Freescale Semiconductor, Inc. ...

Page 47

... VREF_OUT if the VREF_OUT functionality is being used for either an internal or external L reference. 2. The load capacitance should not exceed +/-25% of the nominal specified C the device. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. Unit 1.71 3 ...

Page 48

... Min. Max. Unit 0 50 °C Min. Max. Unit 1.173 1.225 V Freescale Semiconductor, Inc. Unit Notes µ µ Notes Notes ...

Page 49

... Regulator output voltage — Input supply Reg33out (VREGIN) < 3.6 V, pass-through mode C External output capacitor OUT ESR External output capacitor equivalent series resistance K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 0.5 0 14.25 0.25 Min. ...

Page 50

... Max. Unit — 290 — mA Min. Max. Unit 2.7 3.6 V — 25 MHz — ns BUS (t /2) − / SCK SCK ( − — ns BUS − — ns BUS 2 — 8.5 ns −2 — — — ns Freescale Semiconductor, Inc. Notes . Load Notes 1 2 ...

Page 51

... DSPI_SS inactive to DSPI_SOUT not driven DSPI_SS DSPI_SCK (CPOL=0) DSPI_SOUT DS13 DSPI_SIN Figure 18. DSPI classic SPI timing — slave mode K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DS1 DS2 DS8 Data Last data First data DS5 ...

Page 52

... First data DS5 DS6 First data Data Last data Description Table continues on the next page... Max. Unit Notes 3 12.5 MHz — SCK/2) — — — ns — ns — ns DS4 Min. Max. Unit 1.71 3.6 V — 6.25 MHz Freescale Semiconductor, Inc. ...

Page 53

... Set-up time for a repeated START condition Data hold time for I C bus devices 2 Data set-up time Rise time of SDA and SCL signals K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Description DS10 DS15 DS12 First data Data ...

Page 54

... C bus specification) before the SCL line is released SU; DAT f t HD; STA t SU; STA SR t HIGH Fast Mode Unit  Minimum Maximum  +0.1C 300 ns b 0.6 — µs 1.3 — µ ≥ 250 ns must SU; DAT + t rmax SU; DAT BUF SP t SU; STO bus Freescale Semiconductor, Inc. ...

Page 55

... SDHC input hold time IH SDHC_CLK Output SDHC_CMD Output SDHC_DAT[3:0] Input SDHC_CMD Input SDHC_DAT[3:0] K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Card input clock SD3 SD2 SD1 SD6 SD7 SD8 Figure 22. SDHC timing Min ...

Page 56

... S master mode timing (limited voltage range S10 2 S timing — master mode Min. Max. Unit 2.7 3 SYS 45% 55% MCLK period — ns SYS 45% 55% BCLK period — -2.5 — ns — — — — S10 S8 Freescale Semiconductor, Inc. ...

Page 57

... S8 I2S_BCLK to I2S_TXD invalid S9 I2S_RXD/I2S_FS input setup before I2S_BCLK S10 I2S_RXD/I2S_FS input hold after I2S_BCLK K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2 S slave mode timing (limited voltage range) S11 S12 S15 S16 ...

Page 58

... Max. Unit Notes — 3 500 pF 5.5 12.7 MHz 0.5 4.0 MHz 1 1.2 pF 760 mV μ μ 38400 fF/count 38400 fF/count 38400 fF/count — fF/count 10 — 16 bits 15 25 μ — μA 1.3 2.5 μA 12 Freescale Semiconductor, Inc ...

Page 59

... LADJ = — High load (LCD glass capacitance ≤ 8000 pF) • LADJ = — Low load (LCD glass capacitance ≤ 2000 pF) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = 16 μA, REFCHRG = 15, C ref Table 49. LCD electricals Min ...

Page 60

... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 60 Min. Typ. — 0.28 — 2.98 2.0 − 5% 2.0 3.3 − 5% 3.3 3.0 − 5% 3.0 5 − 0. freescale.com and perform a keyword search for the Then use this document number 98ASS23308W Max. Unit Notes — MΩ — MΩ — V — V — V — V Freescale Semiconductor, Inc. ...

Page 61

... VSSA VSSA 26 VREF_OUT/ VREF_OUT/ VREF_OUT/ CMP1_IN5/ CMP1_IN5/ CMP1_IN5/ CMP0_IN5/ CMP0_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_SE18 ADC1_SE18 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 PTE1/ SPI1_SOUT UART1_RX SDHC0_D0 LLWU_P0 PTE2/ SPI1_SCK UART1_CTS_b SDHC0_DCLK ...

Page 62

... EzPort EWM_OUT_b EWM_IN RTC_CLKOUT USB_CLKIN JTAG_TCLK/ EZP_CLK SWD_CLK JTAG_TDI EZP_DI JTAG_TDO/ EZP_DO TRACE_SWO JTAG_TMS/ SWD_DIO NMI_b EZP_CS_b CMP2_OUT I2S0_RX_BCLK JTAG_TRST I2S0_TXD FTM1_QD_ PHA I2S0_TX_FS FTM1_QD_ PHB I2S0_TX_BCLK I2S0_RXD I2S0_RX_FS I2S0_MCLK I2S0_CLKIN LPT0_ALT1 FTM1_QD_ LCD_P0 PHA FTM1_QD_ LCD_P1 PHB Freescale Semiconductor, Inc. ...

Page 63

... VLL1 VLL1 VLL1 78 VCAP2 VCAP2 VCAP2 79 VCAP1 VCAP1 VCAP1 80 PTC4/ LCD_P24 LCD_P24 LLWU_P8 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTB2 I2C0_SCL UART0_RTS_b PTB3 I2C0_SDA UART0_CTS_b PTB7 PTB8 UART3_RTS_b PTB9 SPI1_PCS1 UART3_CTS_b PTB10 ...

Page 64

... UART0_CTS_b FTM0_CH5 PTD6/ SPI0_PCS3 UART0_RX FTM0_CH6 LLWU_P15 PTD7 CMT_IRO UART0_TX FTM0_CH7 ALT5 ALT6 ALT7 EzPort CMP0_OUT LCD_P25 LCD_P26 LCD_P27 LCD_P28 FTM2_FLT0 LCD_P29 LCD_P30 LCD_P31 LCD_P36 LCD_P37 LCD_P38 LCD_P40 LCD_P41 LCD_P42 LCD_P43 EWM_IN LCD_P44 EWM_OUT_b LCD_P45 FTM0_FLT0 LCD_P46 FTM0_FLT1 LCD_P47 Freescale Semiconductor, Inc. ...

Page 65

... VDDA 22 VREFH 23 VREFL 24 VSSA 25 Figure 25. K40 100 LQFP Pinout Diagram 9 Revision History The following table provides a revision history for this document. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Revision History 75 VLL3 VSS 74 73 PTC3 PTC2 72 PTC1 71 PTC0 ...

Page 66

... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 66 Table 50. Revision History footnote in "Voltage and Current Operating Requirements" table. IC spec in "Power consumption operating behaviors" table DD_VBAT description and specs in "USB VREG electrical specifications" table LIM Table continues on the next page... Freescale Semiconductor, Inc. ...

Page 67

... In "SDHC specifications", removed the operating voltage limits and updated the SD1 and SD6 specs. • In "I2S switching specifications", added separate specification tables for the full operating voltage range. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. numbers in 'Power consumption operating behaviors' section. DD_RUN . LAT ...

Page 68

... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time ...

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