MAX1274BCTC

Manufacturer Part NumberMAX1274BCTC
DescriptionAnalog to Digital Converters - ADC
ManufacturerMaxim Integrated
MAX1274BCTC datasheet
 


Specifications of MAX1274BCTC

Number Of Channels1ArchitectureSAR
Conversion Rate1800 KSPsResolution12 bit
Input TypeDifferentialSnr70 dB
Interface TypeQSPI, Serial (SPI, Microwire)Operating Supply Voltage4.75 V to 5.25 V
Maximum Operating Temperature+ 70 CPackage / CaseTQFN EP
Maximum Power Dissipation1349 mWMinimum Operating Temperature0 C
Number Of Converters1Voltage Reference5.25 V
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1.8Msps, Single-Supply, Low-Power,
The SPC register should be written as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
V
L
MAX1274
SCLK
MAX1275
CNVST
DOUT
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
V
L
MAX1274
MAX1275
SCLK
CNVST
DOUT
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
CNVST
SCLK
1
D0
0
0
0
0
DOUT
Figure 17. DSP Interface—Continuous Conversion
______________________________________________________________________________________
True-Differential, 12-Bit ADCs
intervention. Connect the V
supply
MAX1275 are operating with an analog supply voltage
higher than the DSP supply voltage.
The MAX1274/MAX1275 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
DV
DD
The MAX1274/MAX1275 can be directly connected to
TMS320C54_
CLKX
the ADSP21_ _ _ family of DSPs from Analog Devices,
CLKR
Inc. Figure 19 shows the direct connection of the
MAX1274/MAX1275 to the ADSP21_ _ _. There are two
FSX
modes of operation that can be programmed to interface
FSR
with the MAX1274/MAX1275. For continuous conver-
DR
sions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
DV
sions, idle CNVST high and pulse it low for the entire
DD
TMS320C54_
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
ters should be configured for late framing (LAFR = 1)
CLKR
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
FSR
by setting the word length to 8 bits (SLEN = 1001).
Connect the V
DR
when the MAX1274/MAX1275 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
D11
D10
D9
D8
D7
D6
pin to the TMS320C54_
L
voltage
when
the
MAX1274/
DSP Interface to the ADSP21_ _ _
pin to the ADSP21_ _ _ supply voltage
L
D5
D4
D3
D2
D1
D0
0
1
0
15