MAX1274BCTC Maxim Integrated, MAX1274BCTC Datasheet - Page 4

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MAX1274BCTC

Manufacturer Part Number
MAX1274BCTC
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1274BCTC

Number Of Channels
1
Architecture
SAR
Conversion Rate
1800 KSPs
Resolution
12 bit
Input Type
Differential
Snr
70 dB
Interface Type
QSPI, Serial (SPI, Microwire)
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Temperature
+ 70 C
Package / Case
TQFN EP
Maximum Power Dissipation
1349 mW
Minimum Operating Temperature
0 C
Number Of Converters
1
Voltage Reference
5.25 V
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
TIMING CHARACTERISTICS
(V
values are at T
Figure 1. Detailed Serial-Interface Timing
4
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: Digital supply current is measured with the V
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Rise to DOUT Transition
DOUT Remains Valid After SCLK
Rise
CNVST Fall to SCLK Fall
CNVST Pulse Width
Power-Up Time; Full Power-Down
Restart Time; Partial Power-Down
CNVST
DD
DOUT
SCLK
_______________________________________________________________________________________
= +5V ±5%, V
error have been nulled.
ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
t
SETUP
PARAMETER
A
= +25°C.)
L
= V
DD
t
CL
, V
t
DHOLD
t
t
CH
DOUT
REF
= 4.096V, f
SYMBOL
t
t
PWR-UP
t
DHOLD
t
SETUP
t
DOUT
t
CSW
t
t
RCV
CH
CL
SCLK
V
V
C
C
C
V
V
V
= 28.8MHz, 50% duty cycle, T
L
L
L
L
L
L
L
L
= 1.8V to V
= 1.8V to V
= 1.8V to V
= 1.8V to V
= 1.8V to V
= 30pF, V
= 30pF, V
= 30pF, V
IH
t
CSW
level equal to V
L
L
L
DD
DD
DD
DD
DD
= 4.75V to V
= 2.7V to V
= 1.8V to V
CONDITIONS
Figure 2. Load Circuits for Enable/Disable Times
L
, and the V
a) HIGH-Z TO V
DOUT
AND V
DD
DD
6kΩ
DD
OH
TO HIGH-Z
A
OH
= -40°C to +85°C, unless otherwise noted. Typical
IL
, V
level equal to GND.
GND
OL
TO V
OH
,
C
L
15.6
15.6
MIN
10
20
4
TYP
16
2
b) HIGH-Z TO V
DOUT
AND V
OL
6kΩ
MAX
TO HIGH-Z
14
17
24
OL
V
L
, V
C
GND
OH
L
TO V
Cycles
UNITS
ms
ns
ns
ns
ns
ns
ns
OL
,

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