MK22DN512VLK5 Freescale Semiconductor, MK22DN512VLK5 Datasheet - Page 35

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MK22DN512VLK5

Manufacturer Part Number
MK22DN512VLK5
Description
ARM Microcontrollers - MCU ARM+512Kb +USB
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK22DN512VLK5

Rohs
yes
Core
ARM Cortex M4
Processor Series
MK22DN512
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

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4.5.1
4.5.1.1 ARM Cortex-M4 Core
4.5.1.2 Nested Vectored Interrupt Controller (NVIC)
4.5.1.3 Wake-up Interrupt Controller (WIC)
4.5.1.4 Debug Controller
Freescale Semiconductor, Inc.
• Supports up to 120 MHz frequency with 1.25DMIPS/MHz
• ARM Core based on the ARMv7 Architecture & Thumb
• Microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments
• Harvard bus architecture
• 3-stage pipeline with branch speculation
• Integrated bus matrix
• Integrated Digital Signal Processor (DSP)
• Configurable nested vectored interrupt controller (NVIC)
• Advanced configurable debug and trace components
• Embedded Trace Macrocell (ETM)
• Close coupling with Cortex-M4 core's Harvard architecture enables low latency interrupt handling
• Up to 120 interrupt sources
• Includes a single non-maskable interrupt
• 16 levels of priority, with each interrupt source dynamically configurable
• Supports nesting of interrupts when higher priority interrupts are activated
• Relocatable vector table
• Supports interrupt handling when system clocking is disabled in low power modes
• Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very-deep-sleep
• A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked
• Contains no programmer’s model visible state and is therefore invisible to end users of the device other than through
• Serial Wire JTAG Debug Port (SWJ-DP) combines
• Debug Watchpoint and Trace (DWT) with the following functionality:
• Instrumentation Trace Macrocell (ITM) with the following functionality:
• Embedded Trace Macrocell (ETM) supports instruction trace
interrupt is detected
the benefits of reduced power consumption while sleeping
• external interface that provides a standard JTAG or cJTAG interface for debug access
• external interface that provides a serial-wire bidirectional debug interface
• four comparators configurable as a hardware watchpoint, an ETM trigger, a PC sampler event trigger, or a data
• several counters or a data match event trigger for performance profiling
• configurable to emit PC samples at defined intervals or to emit interrupt event information
• Software trace - writes directly to ITM stimulus registers can cause packets to be emitted
• Hardware trace - packets generated by DWT are emitted by ITM
• Time stamping - emitted relative to packets
Core modules
address sampler event trigger
K20 Family Product Brief, Rev. 11, 08/2012
®
-2 ISA
Core modules
35

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