MK22DX128VMC5

Manufacturer Part NumberMK22DX128VMC5
DescriptionARM Microcontrollers - MCU ARM+128KB +USB
ManufacturerFreescale Semiconductor
MK22DX128VMC5 datasheet
 

Specifications of MK22DX128VMC5

RohsyesCoreARM Cortex M4
Processor SeriesK20Data Bus Width32 bit
Maximum Clock Frequency50 MHzProgram Memory Size128 KB
Data Ram Size32 KBOn-chip AdcYes
Operating Supply Voltage1.71 V to 3.6 VOperating Temperature Range- 40 C to + 85 C
Package / CaseMAPBGA-121Mounting StyleSMD/SMT
A/d Bit Size16 bitInterface TypeI2C, I2S, SPI, UART, USB
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Number Of Programmable I/os16Number Of Timers4
On-chip DacYesProgram Memory TypeFlash
Supply Voltage - Max3.6 VSupply Voltage - Min1.71 V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
Page 44/55

Download datasheet (2Mb)Embed
PrevNext
Communication interfaces
• Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 bytes data length each, configurable as Rx
or Tx, all supporting standard and extended messages
• Listen-only mode capability
• Individual mask registers for each message buffer
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• Timestamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
4.5.7.6 Serial Peripheral Interface (SPI)
• Master and slave mode
• Full-duplex, three-wire synchronous transfers
• Programmable transmit bit rate
• Double-buffered transmit and receive data registers
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8-bit or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed transfers of large amounts of data
• Support for both transmit and receive by DMA
4.5.7.7 Inter-Integrated Circuit (I
2
• Compatible with I
C bus standard and SMBus Specification Version 2 features
• Up to 100 kbps with maximum bus loading
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Programmable slave address and glitch input filter
• Interrupt or DMA driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection broadcast and 10-bit address extension
• Address matching causes wake-up when processor is in low power mode
4.5.7.8 UART
• Support for ISO 7816 protocol for interfacing with smartcards
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width
• 13-bit baud rate selection with fractional divide of 32
• Programmable 8-bit or 9-bit data format
• Separately enabled transmitter and receiver
• Programmable transmitter output polarity
• Programmable receive input polarity
• 13-bit break character option
• 11-bit break character detection option
• Parameterizable buffer support for one dataword for each transmit and receive
• Independent FIFO structure for transmit and receive
• Two receiver wakeup methods:
K20 Family Product Brief, Rev. 11, 08/2012
44
2
C)
Freescale Semiconductor, Inc.