MPXN2120VMG116 Freescale Semiconductor, MPXN2120VMG116 Datasheet

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... Analog to Digital Converter (ADC) module – 10-bit A/D resolution – 32 external channels – 36 internal channels (PXN20) – 64 internal channels (PXN21) • Cross-Triggering Unit (PXN21 only) © Freescale Semiconductor, Inc., 2011. All rights reserved. Document Number: PXN20 PXN20 PXN21 MAPBGA–208 • ...

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... Operating current specifications 4.7 I/O pad current specifications . . . . . . . . . . . . . . . . . . . 34 4.8 Low voltage characteristics . . . . . . . . . . . . . . . . . . . . . 36 4.9 Oscillators electrical characteristics 4.10 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 38 4.11 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 39 4.12 Flash memory electrical characteristics . . . . . . . . . . . 39 4.13 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.14 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5 Package characteristics 5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 58 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PXS30 Microcontroller Data Sheet, Rev Freescale Semiconductor ...

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... V = –40 °C to 105 °C (ambient) Note: Not all options are available on all devices. See Figure 1. PXN20 orderable part number description Table 1. PXN20 orderable part number summary Part number MPXN2020VMG116 MPXN2120VMG116 1.2 PXN20 family feature set Feature Central Processing Unit (CPU) Cache Floating Point Unit (FPU) ...

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... Supports 32 external channels 32 channels, 16-bit No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 8 8 Yes Yes Yes Yes 155 155 Yes Yes Yes Yes Nexus3 (e200Z6) Nexus2+ (e200Z0) 208 MAPBGA 256 MAPBGA Freescale Semiconductor ...

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... FlexRay™ – FlexRay bus controller FMPLL – Frequency-modulated phase-locked loop – Inter-integrated circuit controller INTC – Interrupt controller JTAG – Joint Test Action Group interface Freescale Semiconductor 32 kHz XTAL 128 kHz IRC VLE Semaphores 16-ch DMA Ethernet Mux Crossbar Switch (XBAR) ...

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... Memory protection unit – Nexus debug interface – Periodic interrupt timer – Real time clock – System integration unit – Serial peripheral interface controller – System timer module – Software watchdog timer local interconnect network – Voltage regulator Freescale Semiconductor ...

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... PE10 PE11 N PF8 PF5 TCK PE12 P PF10 R PF7 PF11 PK4 V PF9 PK3 PK5 Figure 4. PXN20 208-ball MAPBGA (full diagram) Freescale Semiconductor PC9 PC7 PC2 PB13 PB10 PB8 RESET PC10 PC8 PC3 PB14 PB11 V V RCCTL RC ...

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... Type During After 6 7 Reset Reset V IHA — — DDA V IHA — — DDA V IHA — — DDA V IHA — — DDA V IHA — — DDA V IHA — — DDA Freescale Semiconductor 5). 208 BGA D15 E15 F16 F15 G16 G15 ...

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... Port A GPI AN[14] 01 ADC Analog Input EXTAL32 10 External 32 kHz Crystal In 11 — PA15 PA[15 Port A GPI AN[15] 01 ADC Analog Input XTAL32 10 External 32 kHz Crystal Out 11 — Freescale Semiconductor I/O Description Type I I — — — — — — — — — ...

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... DDE1 SHA — — DDE1 SHA — — DDE1 SHA — — DDE1 SHA — — DDE1 SHA — — DDE1 SHA — — DDE1 Freescale Semiconductor 208 BGA B14 C14 B13 C13 C12 D12 C11 D11 A10 B12 ...

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... ADC Analog Input 10 — 11 — PC2 PC[ Port C GPIO AN[34] 01 ADC Analog Input EVTI 10 Nexus Event In 11 — PC3 PC[ Port C GPIO AN[35] 01 ADC Analog Input EVTO 10 Nexus Event Out 11 — Freescale Semiconductor I/O Description Type I — I — I — I — I — I/O V ...

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... SHA — — DDE1 V SHA — — DDE1 V SHA — — DDE1 V SHA — — DDE1 V SHA — — DDE1 V SHA — — DDE1 V SHA — — DDE1 V SHA — — DDE1 Freescale Semiconductor 208 BGA ...

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... PD7 PD[ Port D GPIO CNRX_D 01 FlexCAN_D Receive RXD_K 10 SCI_K Receive SDA_B 11 I PD8 PD[ Port D GPIO CNTX_E 01 FlexCAN_E Transmit TXD_L 10 SCI_L Transmit SCL_C 11 I Freescale Semiconductor I/O Description Type I — Port D (16) I/O O — — I/O I — — I/O O — — I/O I — — I/O O — ...

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... V SH — — DDE2 V SH — — DDE2 V SH — — DDE2 V SH — — DDE2 V SH — — DDE2 V SH — — DDE2 V SH — — DDE2 V SH — — DDE2 Freescale Semiconductor 208 BGA ...

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... DSPI_B Peripheral Chip Select 11 — PE12 PE[12 Port E GPIO TXD_J 01 eSCI_J Transmit PCS_C[5] 10 DSPI_C Peripheral Chip Select 11 — PE13 PE[13 Port E GPIO RXD_J 01 eSCI_J Receive PCS_C[3] 10 DSPI_C Peripheral Chip Select 11 — Freescale Semiconductor I/O Description Type I I/O I I/O I I/O I I/O I I/O I I/O ...

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... V MH — — DDE2 V MH — — DDE2 V SH — — DDE2 V SH — — DDE2 V MH — — DDE2 V MH — — DDE2 V SH — — DDE2 V SH — — DDE2 Freescale Semiconductor 208 BGA ...

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... DSPI_A Peripheral Chip Select PCS_B[3] 10 DSPI_B Peripheral Chip Select AN[48] 11 ADC Analog Input PG1 PG[ Port G GPIO PCS_A[5] 01 DSPI_A Peripheral Chip Select PCS_B[4] 10 DSPI_B Peripheral Chip Select AN[49] 11 ADC Analog Input Freescale Semiconductor I/O Description Type I/O V I/O — — I — — I — — I/O V ...

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... DDE3 V MHA — — DDE3 V SHA — — DDE3 V SHA — — DDE3 V MHA — — DDE3 V SHA — — DDE3 V MHA — — DDE3 Freescale Semiconductor 208 BGA H14 J14 K14 L14 H15 J15 K15 L15 M15 J16 K16 ...

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... Ethernet Receive Data 11 — PH5 PH[5] 117 00 Port H GPIO eMIOS[26] 01 eMIOS Channel FEC_RXD[1] 10 Ethernet Receive Data 11 — PH6 PH[6] 118 00 Port H GPIO eMIOS[25] 01 eMIOS Channel FEC_RXD[2] 10 Ethernet Receive Data 11 — Freescale Semiconductor I/O Description Type I I I Port H (16) I/O V I/O I — I/O V I/O I — ...

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... Reset SH — — DDE3 SH — — DDE4 SH — — DDE4 SH — — DDE4 SH — — DDE4 SH — — DDE4 SH — — DDE4 SH — — DDE4 SH — — DDE4 SH — — DDE4 Freescale Semiconductor 208 BGA T15 P10 P11 N11 R7 ...

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... Port J GPIO eMIOS[06] 01 eMIOS Channel 10 — 11 — PJ10 PJ[10] 138 00 Port J GPIO eMIOS[05] 01 eMIOS Channel 10 — 11 — PJ11 PJ[11] 139 00 Port J GPIO eMIOS[04] 01 eMIOS Channel 10 — 11 — Freescale Semiconductor I/O Description Type I/O V I/O O — I/O V I/O O — I/O V I/O O — I/O V I/O O — I/O V I/O O — I/O V I/O O — ...

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... DDE4 SH — — DDE4 SH — — DDE4 SH — — DDE4 F — — DDEMLB F — — DDEMLB F — — DDEMLB SH — — DDE2 MH — — DDE2 MH — — DDE2 Freescale Semiconductor 208 BGA R12 T12 R13 T13 ...

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... The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number. 4 The PA bitfield in the SIU_PCRn register selects the signal function for the pin. A dash in the Description field of this table indicates that this value for PC is reserved on this pin, and should not be used. Freescale Semiconductor I/O Description Type ...

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... A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. 8 Pullup is enabled only when JCOMP is negated. 9 Tie to V for normal operation PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor ...

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... RH V Analog Low Voltage Reference Analog Ground SSA V Clock Synthesizer Ground SSSYN 1 Nominal voltages. 2 Base current to external NPN power transistor. Voltage may vary. Freescale Semiconductor Table 4. PXN20 power/ground Voltage 1.2 V 3.3–5.0 V 3.3–5.0 V 3.3 V 2 SSA 3.3–5.0 V — 3.3 V 3.3–5 ...

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... V + 0.3 V DDEx V –0.3 Minimum 0.3 DDA V –0.3 5.5 RL – V –100 100 SSA – V –100 100 SSSYN I –2 2 MAXD I –3 3 MAXA T –55.0 150.0 STG T — 235.0 SDR MSL — 3 Freescale Semiconductor Unit ...

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... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 4.2.1 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, T Freescale Semiconductor is within Operating Voltage specifications. DDE Table 6. Thermal characteristics Symbol R JA R  ...

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... For instance, the user can change the air flow around the device, add a heat sink, change the  C/W)   C/W) o C/W) per JESD51 JA JC CA o C/W) o C/W) o C/W) PXN20 Microcontroller Data Sheet, Rev. 1 Eqn. 2 Eqn. 3 Freescale Semiconductor ...

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... G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998 Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220. Freescale Semiconductor  ( ...

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... V 250 (all other pins) 1 — 1 — 1 second Symbol Min Max I_V 6.25 µ RCCTL BETA 500 Symbol Min Max T –40.0 150 3.0 3.6 DDSYN V 3.0 3.6 DD33 V VRC 3.0 3.6 4.5 5.5 V maximum of 5.5 DDA 3 – 0.1 VRC Freescale Semiconductor Units — Unit ...

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... DDEx DDSYN pins 27 Capacitive Supply Load ( Capacitive Supply Load (V DD33 1 When (low), V RCSEL SSA DDSYN generated by internal voltage regulators. When V Freescale Semiconductor Table 9. DC electrical specifications (Analog pins IHA and V power supply ...

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... DDEH = 3.0 V DDEH 1 1 Typ Max 25 C –40–150 C Symbol Ambient Junction — — — I DDE 0 30 Note DDA + 300 700 DD33 Freescale Semiconductor Unit —  A A A A mA A ...

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... Sleep mode draws 1 .A (typ). With the optional 4–40 MHz osc enabled w/ no clock, add DDSYN 150 .A for a total of 151 .A (typ Current excluding the current supply Maximum supply current transition: 50mA per 20S observation window. Freescale Semiconductor Table 10. Operating currents (continued) Characteristic DD33 DDSYN ...

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... Table PXN20 Microcontroller Data Sheet, Rev. 1 Table 11 1 Drive/Slew I Avg I DDE DDE Rate Select (mA 5 2.5 00 0.5 00 1.5 11 50.4 10 14.2 01 16.4 00 9.8 11 22.9 10 6 N/A N/A 3. Freescale Semiconductor based on RMS (mA) 101.6 57.3 43.6 15.9 45.3 25.3 17.3 9.6 N/A ...

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... These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. 2 Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See 3 All loads are lumped. Freescale Semiconductor current specifications supply is dependent on the usage of the pins on all I/O segments. The power consumption currents for all I/O segments. The output pin V DD33 Table 12 ...

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... Min Typical Max 1.5 — 2.8 3.00 3.05 3.10 3.04 3.12 3.19 3.00 3.05 3.10 3.04 3.12 3.19 3.00 3.05 3.10 3.04 3.12 3.19 3.25 3.35 3.48 3.35 3.45 3.55 4.35 4.475 4.55 4.45 4.575 4.65 4.50 4.675 4.80 4.50 4.675 4.80 Min Max 0 0.3 XTAL DDSYN 0.65  0.3 DDSYN DDSYN V – 0.3 V – 0.4 DDSYN XTAL 0.35  – 0.3 DDSYN DDSYN 1 3 — 3 — 3 Freescale Semiconductor Unit Unit MHz % ...

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... Frequency before trim 2 Frequency after loading factory trim 3 3 Application trim resolution 4 Application frequency trim step 5 Startup Time 1 Across process, voltage, and temperature. 2 Across voltage and temperature. 3 Fixed voltage and temperature. Freescale Semiconductor Symbol C See crystal L specification C L_EXTAL C L_XTAL t startup Symbol f ref32 t ...

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... ERFD + 1 100 2000 16 64 MHz — 400 –4.0 4 –2.0 2.0 %f –5 5 –250 250 % –0.50 0.50 %f 192 600 MHz 0.400 1 MHz Freescale Semiconductor Unit kHz kHz % kHz s Unit kHz s % SYS SYS SYS ns SYS SYS ...

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... Double Word (64 bits) Program Time 2 Page (128 bits and 256 bits) Program Time Block Pre-program and Erase Time Block Pre-program and Erase Time 5 128 KB Block Pre-program and Erase Time Freescale Semiconductor value greater than the f PLL PLL . SYS Symbol V RH ...

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... SYS t — — 45 Recover Symbol Min Typical Unit P/E 100,000 — cycles P/E 1,000 100,000 cycles Retention — years – 5,6 Rise/Fall Load Drive (ns) (pF) 155/173 50 188/204 200 30/34 50 38/44 200 10/11 50 15/17 200 Freescale Semiconductor ms s ...

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... Add a maximum of one system clock to the output delay for delay with respect to system clock. 8 Output delay is shown in. Add a maximum of one system clock to the output delay for delay with respect to system clock. Table 24. De-rated pad AC specifications (3 Spec Pad Type 7 1 Slow 2 Medium Freescale Semiconductor 3 4,4 SRC/DSC Output Delay (ns) 142/186 00 195/253 20/35 01 41/64 ...

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... DDE DDEH Table Rising Edge Out Delay Pad Output Figure 6. Pad output delay PXN20 Microcontroller Data Sheet, Rev (continued) 4,5 6, Rise/Fall Load Drive (ns) 1.2 1.2 1.2 1.2 1.5/1.5 and V = 3.0 – 3 RC33 DDPLL 3. Falling Edge Out Delay Freescale Semiconductor (pF 0 VDD ...

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... IRQ/NMI Pulse Width High 1 3 IRQ/NMI Edge to Edge Time 1 Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both. IRQ/NMI 1,2 Freescale Semiconductor Characteristic 1 Table 26. IRQ/NMI timing Symbol 1,2 3 Figure 8. IRQ and NMI timing PXN20 Microcontroller Data Sheet, Rev. 1 ...

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... TDOI t — 20 TDOHZ t 100 — JCMPPW t 40 — JCMPS t — 50 BSDV t — 50 BSDVZ t — 50 BSDHZ t 50 — BSDST t 50 — BSDHT = 3.0 – 5 DDE Freescale Semiconductor Unit and ...

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... TCK TMS, TDI TDO Figure 10. JTAG Test Access Port (TAP) timing TCK JCOMP Freescale Semiconductor Figure 11. JTAG JCOMP timing PXN20 Microcontroller Data Sheet, Rev. 1 Electrical characteristics ...

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... Electrical characteristics TCK Output Signals Output Signals Input Signals Figure 12. JTAG boundary scan timing PXN20 Microcontroller Data Sheet, Rev Freescale Semiconductor ...

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... This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). D_CLKOUT eMIOS output eMIOS input Freescale Semiconductor Table 28. eMIOS timing Characteristic = and with SRC = 0b11 ...

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... PASC t SUI 25 — 5 — 10 — 25 — –4 — 7 — 12 — –4 — t SUO — 8 — 28 — 15 — –7 — 2 — 1 — –7 — Freescale Semiconductor Unit ...

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... SIN SOUT Figure 14. DSPI classic SPI timing — Master, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 15. DSPI classic SPI timing — Master, CPHA = 1 Freescale Semiconductor Last Data First Data Data 12 11 First Data ...

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... Figure 17. DSPI classic SPI timing — Slave, CPHA = First Data Data Last Data 9 10 Data Last Data First Data 11 5 Data First Data 9 10 Data First Data PXN20 Microcontroller Data Sheet, Rev Last Data Last Data Freescale Semiconductor ...

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... SIN SOUT Figure 18. DSPI modified transfer format timing — Master, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 19. DSPI modified transfer format timing — Master, CPHA = 1 Freescale Semiconductor First Data Last Data Data 12 11 First Data ...

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... First Data Data Last Data 10 9 Data First Data Last Data 11 5 First Data Data 9 10 First Data Data 7 Figure 22. DSPI PCS strobe (PCSS) timing PXN20 Microcontroller Data Sheet, Rev Last Data Last Data 8 Freescale Semiconductor ...

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... MLBCLK rise time 3 MLBCLK fall time 4 MLBCLK cycle time 5 MLBCLK low time 6 MLBCLK high time 7 MLBCLK pulse width variation 8 MLBSIG/MLBDAT input valid to MLBCLK falling 9 MLBSIG/MLBDAT input hold from MLBCLK low Freescale Semiconductor Symbol Min Typ — — — V — — 1.8 — — ...

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... Fs at 48.0 kHz 49.2544 MHz 1024 Fs at 48.1 kHz 51.200 1024 Fs PLL unlocked — — ns 1024 Fs PLL unlocked — ns 1024 Fs PLL unclocked 0.7 ns p-p — ns — mckl — Table 30. Freescale Semiconductor ...

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... In addition, the system clock frequency must exceed four times the RX_CLK frequency. Spec M1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup M2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold M3 RX_CLK pulse width high M4 RX_CLK pulse width low Freescale Semiconductor valid data valid data Figure 23. Media Local Bus (MLB) timing Table 33. MII receive signal timing Characteristic PXN20 Microcontroller Data Sheet, Rev ...

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... Table 34. MII transmit signal timing Characteristic Table 35. MII Async Inputs Signal Timing Characteristic PXN20 Microcontroller Data Sheet, Rev Min Max Unit 5 — ns — 35% 65% TX_CLK period 35% 65% TX_CLK period M8 1 Min Max Unit 1.5 — TX_CLK period Freescale Semiconductor ...

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... MDC pulse width high M15 MDC pulse width low 1 Output pads configured with SRC = 0b11. MDC (output) MDIO (output) MDIO (input) Figure 27. MII serial management channel timing diagram Freescale Semiconductor M9 Figure 26. MII async inputs timing diagram Characteristic M14 M10 M11 M12 M13 PXN20 Microcontroller Data Sheet, Rev ...

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... Package characteristics 5 Package characteristics 5.1 Package mechanical data Figure 28. 208 MAPBGA package mechanical drawing 58 PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor ...

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... Freescale Semiconductor Figure 29. 208 MAPBGA package detail PXN20 Microcontroller Data Sheet, Rev. 1 Package characteristics 59 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...