STM32F051K8T6 STMicroelectronics, STM32F051K8T6 Datasheet
STM32F051K8T6
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STM32F051K8T6 Summary of contents
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Low- and medium-density advanced ARM™-based 32-bit MCU with Kbytes Flash, timers, ADC, DAC and comm. interfaces Features ■ Operating conditions: – Voltage range: 2 3.6 V ■ ARM 32-bit Cortex®-M0 CPU (48 MHz max) ■ ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F051x 3.19 Analog to digital converter (ADC 3.19.1 ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F051x List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STM32F051xx family incorporates the high-performance ARM Cortex™-M0 32-bit RISC core operating MHz frequency, high-speed embedded memories (Flash memory Kbytes and SRAM Kbytes), and an extensive range of ...
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STM32F051x Table 2. STM32F051xx family device features and peripheral counts Peripheral Flash (Kbytes) 16 SRAM (Kbytes) Advanced control Timers General purpose Basic (1) SPI (I2S) 1( Comm. interfaces (4) USART 1 CEC 12-bit synchronized ADC (number of ...
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Device overview 2 Device overview Figure 1. Block diagram 8/9 Doc ID 018746 Rev 2 STM32F051x ...
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STM32F051x Figure 2. Clock tree Doc ID 018746 Rev 2 Device overview 9/9 ...
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Functional overview 3 Functional overview ® 3.1 ARM Cortex The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with ...
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STM32F051x 3.4 Direct memory access controller (DMA) The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each ...
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Functional overview 3.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it ...
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STM32F051x The device features an embedded programmable voltage detector (PVD) that monitors the V power supply and compares it to the V DD when V drops below the V DD threshold. The interrupt service routine can then generate a warning ...
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Functional overview 3.11 Real-time clock (RTC) and backup registers The RTC and the 5 backup registers are supplied through a switch that takes power either on V supply when present or through the V DD registers used to store 20 ...
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STM32F051x 3.12 Timers and watchdogs The STM32F051xx family devices include up to six general-purpose timers, one basic timer and an advanced control timer. Table 3 compares the features of the advanced-control, general-purpose and basic timers. Table 3. Timer feature comparison ...
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Functional overview 3.12.2 General-purpose timers (TIM2..3, TIM14..17) There are six synchronizable general-purpose timers embedded in the STM32F051xx devices (see Table 3 PWM outputs simple time base. TIM2, TIM3 STM32F051xx devices feature two synchronizable 4-channel general-purpose timers. TIM2 is ...
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STM32F051x 3.12.4 Independent window watchdog (IWWDG) The independent window watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window clocked from an independent 40 kHz internal RC and as it operates independently from the ...
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Functional overview In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. I2C1 also has a clock domain independent from the CPU clock, ...
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STM32F051x Table 6. STM32F051xx USART implementation USART modes/features Hardware flow control for modem Continuous communication using DMA Multiprocessor communication Synchronous mode Smartcard mode Single-wire half-duplex communication IrDA SIR ENDEC block LIN mode Dual clock domain and wakeup from Stop mode ...
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Functional overview 3.16 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The device embeds a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control ...
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STM32F051x Table 9. No. of capacitive sensing channels available on STM32F051xx devices Analog I/O group Number of capacitive sensing channels 3.19 Analog to digital converter (ADC) The 12-bit analog to digital converter has up ...
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Functional overview 3.20 Digital-to-analog converter (DAC) The 12-bit buffered DAC channel can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This ...
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STM32F051x 4 Pinouts and pin description Figure 3. LQFP64 64-pin package pinout Doc ID 018746 Rev 2 Pinouts and pin description 23/30 ...
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Pinouts and pin description Figure 4. LQFP48 48-pin package pinout Figure 5. UFQFPN32 32-pin package pinout 24/30 Doc ID 018746 Rev 2 STM32F051x ...
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STM32F051x Table 10. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Alternate functions Pin functions Additional functions Table 11. Pin definitions Pin number Pin name (function after reset VBAT 2 2 PC13 ...
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Pinouts and pin description Table 11. Pin definitions (continued) Pin number Pin name (function after reset) 8 PC0 9 PC1 10 PC2 11 PC3 VSSA VDDA PA0 PA1 ...
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STM32F051x Table 11. Pin definitions (continued) Pin number Pin name (function after reset PB1 PB2 29 21 PB10 30 22 PB11 VSS VDD 33 25 PB12 34 26 ...
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Pinouts and pin description Table 11. Pin definitions (continued) Pin number Pin name (function after reset) PA14 (SWCLK PA15 51 PC10 52 PC11 53 PC12 54 PD2 PB3 ...
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Table 12. Alternate functions selected through GPIOA_AFR registers for port A Pin name AF0 AF1 PA0 USART2_CTS PA1 EVENTOUT USART2_RTS PA2 TIM15_CH1 USART2_TX PA3 TIM15_CH2 USART2_RX SPI1_NSS/ PA4 USART2_CK I2S1_WS SPI1_SCK/ PA5 CEC I2S1_CK SPI1_MISO/ PA6 TIM3_CH1 I2S1_MCK SPI1_MOSI/ PA7 ...
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Table 13. Alternate functions selected through GPIOB_AFR registers for port B Pin name AF0 PB0 EVENTOUT PB1 TIM14_CH1 PB2 PB3 SPI1_SCK/I2S1_CK PB4 SPI1_MISO/I2S1_MCK PB5 SPI1_MOSI/I2S1_SD PB6 USART1_TX PB7 USART1_RX PB8 CEC PB9 IR_OUT PB10 CEC PB11 EVENTOUT PB12 SPI2_NSS PB13 ...
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STM32F051x 5 Memory mapping Figure 6. STM32F051x memory map Doc ID 018746 Rev 2 Memory mapping 31/33 ...
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Memory mapping Table 14. STM32F051x peripheral register boundary addresses Bus AHB2 AHB1 APB 32/33 Boundary address 0x4800 1800 - 0x5FFF FFFF 0x4800 1400 - 0x4800 17FF 0x4800 1000 - 0x4800 13FF 0x4800 0C00 - 0x4800 0FFF 0x4800 0800 - 0x4800 ...
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STM32F051x Table 14. STM32F051x peripheral register boundary addresses (continued) Bus APB Boundary address 0x4000 7C00 - 0x4000 7FFF 0x4000 7800 - 0x4000 7BFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 5C00 - 0x4000 6FFF 0x4000 5800 ...
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Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...
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STM32F051x Figure 7. LQFP64 – pin low-profile quad flat package outline Pin 1 identification Drawing is not to scale. 2. Dimensions are ...
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Package characteristics Figure 9. LQFP48 – 7mm, 48-pin low-profile quad flat package outline Pin 1 identification Drawing is not to scale. 2. Dimensions are in ...
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STM32F051x Figure 11. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (1)(2)( Seating plane Pin # 0.30 D2 Bottom ...
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Ordering information scheme 7 Ordering information scheme For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Example: Device family STM32 = ...
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STM32F051x 8 Revision history Table 18. Document revision history Date 09-Feb-2012 14-Feb-2012 Revision 1 Initial release Added Table 2: STM32F051xx family device features and peripheral counts 2 Updated Table 7: STM32F051x SPI/I2S implementation Doc ID 018746 Rev 2 Revision history ...
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