MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet

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MPC8543VTANGA

Manufacturer Part Number
MPC8543VTANGA
Description
Microprocessors - MPU PQ3 8543
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8543VTANGA

Product Category
Microprocessors - MPU
Rohs
yes
Processor Series
PowerQUICC III
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
BGA
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Freescale Semiconductor
Data Sheet: Technical Data
MPC8548E PowerQUICC III
Integrated Processor
Hardware Specifications
1
This section provides a high-level overview of the device
features. The following figure shows the major functional
units within the device.
Although this document is written from the perspective of
the MPC8548E, most of the material applies to the other
family members, such as MPC8547E, MPC8545E, and
MPC8543E. When specific differences occur, such as pinout
differences and processor frequency ranges, they are
identified as such.
For specific PVR and SVR numbers, see the MPC8548E
PowerQUICC III Integrated Host Processor Reference
Manual.
© 2012 Freescale Semiconductor, Inc. All rights reserved.
Overview
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11. Programmable Interrupt Controller . . . . . . . . . . . . . 53
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13. I
14. GPOUT/GPIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15. PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 65
17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
18. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
19. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 91
20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
22. System Design Information . . . . . . . . . . . . . . . . . . 135
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 145
24. Document Revision History . . . . . . . . . . . . . . . . . . 148
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 20
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8. Enhanced Three-Speed Ethernet (eTSEC) . . . . . . . . 27
9. Ethernet Management Interface Electrical
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Document Number: MPC8548E
Contents
Rev. 9, 02/2012

Related parts for MPC8543VTANGA

MPC8543VTANGA Summary of contents

Page 1

... For specific PVR and SVR numbers, see the MPC8548E PowerQUICC III Integrated Host Processor Reference Manual. © 2012 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8548E Rev. 9, 02/2012 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10 3 ...

Page 2

... PCI Bus Interface (If 64-bit not used) 64-bit PCI/PCI-X 4-Channel DMA Figure 1. Device Block Diagram e500 Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Cache Cache or 4x RapidIO PCI Express x8 PCI Express PCI 32-bit 66 MHz 32-bit PCI/ PCI/PCI-X 133 MHz Bus Interface Controller Freescale Semiconductor ...

Page 3

... Four banks of memory supported, each Gbytes maximum of 16 Gbytes — DRAM chip configurations from 64 Mbits to 4 Gbits with ×8/×16 data ports — Full ECC support — Page mode support – simultaneous open pages for DDR MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Overview 3 ...

Page 4

... DEU—Data Encryption Standard execution unit – DES, 3DES – Two key (K1, K2) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev and F(p) modes and programmable field size Freescale Semiconductor ...

Page 5

... The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. — Three protocol engines available on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 2 C addressing mode Overview 2 ...

Page 6

... CRC generation and verification of inbound/outbound frames — Programmable Ethernet preamble insertion and extraction bytes — MAC address recognition: – Exact match on primary and virtual 48-bit unicast addresses MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Section 8.1, “Enhanced for Freescale Semiconductor ...

Page 7

... Host and agent mode support — 64-bit dual address cycle (DAC) support — PCI-X supports multiple split transactions — Supports PCI-to-memory and memory-to-PCI streaming MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Overview 7 ...

Page 8

... Capable of receiving three letters at any mailbox — Two outbound data message structures within the outbox — Capable of sending three letters simultaneously — Single segment multicast devIDs — Chaining and direct modes in the outbox MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 9

... Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download • JTAG boundary scan, designed to comply with IEEE Std. 1149.1™ MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Overview 9 ...

Page 10

... V –0.3 to 1.98 –0.3 to 3.63 V –0.3 to 2.75 –0.3 to 3.63 –0.3 to 2.75 –0.3 to 3.63 V — –0.3 to 3.63 V — –0.3 to 2.75 –0.3 to ( –0 — ( 0.3) DD –0.3 to ( –0.3 to (TV + 0.3) DD –0.3 to (BV + 0.3) — — DD –0.3 to ( –0.3 to ( Freescale Semiconductor ...

Page 11

... DDR and DDR2 DRAM reference Three-speed Ethernet signals Local bus signals PCI, DUART, SYSCLK, system control and power 2 management Ethernet MII management, and JTAG signals MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 1 (continued) Symbol Max Value T –55 to 150 STG Table 2 ...

Page 12

... CLOCK references MCLK. references EC_GTX_CLK125. CLOCK references LCLK. references PCIn_CLK or SYSCLK. references SD_REF_CLK. CLOCK Recommended Symbol Unit Value  105 and not necessarily the voltage 1 CLOCK /OV /LV /BV / Table and LV DD Freescale Semiconductor Notes — 2. The based DD REF ...

Page 13

... GV is required. If there is no concern about any of the DDR signals being indeterminate state during power-up, then the sequencing for GV not required. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Table 3. Output Drive Capability Programmable Output Impedance ( ...

Page 14

... From a system standpoint, if any of the I/O power supplies ramp prior to the V core supply, the I/Os associated with that I/O supply may drive a logic DD one or zero during power-up, and extra current may be drawn by the device. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE Freescale Semiconductor ...

Page 15

... CCB frequency is the SoC platform frequency, which corresponds to the DDR data rate. 2. SLEEP is based 1 Typical-65 is based 1 Typical-105 is based 1 Maximum is based 1 MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Table 4. Device Power Dissipation 2 SLEEP Typical-65 2.7 4.6 2.7 5.0 2.7 5.4 11.5 13.6 6.2 7.9 = 65 ...

Page 16

... SYSCLK — — and , and minimum clock low time is 2  t CCB . Typ Max Unit — 133 MHz — 1.0 1.2 ns — — ±150 ps Section 20.3, “e500 Core PLL Ratio,” . There is CCB Freescale Semiconductor Notes for ratio ...

Page 17

... PCIn_CLK cycle time PCIn_CLK rise and fall time PCIn_CLK duty cycle Notes: 1. Rise and fall times for SYSCLK are measured at 0.6 and 2 Timing is guaranteed by design and characterization. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Symbol Min f — G125 t — ...

Page 18

... Section 17.4, “1x/4x LP-Serial Signal Descriptions,” for serial RapidIO interface width and frequency details. 4.7 Other Input Clocks For information on the input clocks of other functional blocks of the platform see the specific section of this document. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev 527 MHz  (PCI-Express link width Freescale Semiconductor ...

Page 19

... AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD. Their ramp rates must be equal to or less than the VDD ramp rate. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Table 9. PLL Lock Times Table 10. Power Supply Ramp Rate Min — ...

Page 20

... V for DDR2 SDRAM. DD (typ Max Unit 1.89 V 0.51  0.04 V REF – 0.125 V REF A 50 — mA — (typ)=1 Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT Freescale Semiconductor Notes — — 4 — — Notes 1 1 ...

Page 21

... This table provides the current draw characteristics for MV Table 15. Current Draw Characteristics for MV Parameter/Condition Current draw for MV REF Note: must be able to supply up to 500 A current. 1. The voltage regulator for MV REF MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Symbol Min GV 2.375 DD 0.49  REF V MV – ...

Page 22

... T is the clock period and abs(t DISKEW CISKEW (typ Min Max — MV – 0.25 REF MV + 0.25 — REF (typ Min Max — MV – 0.31 REF MV + 0.31 — REF Max Unit Notes ps 300 365 390 . This can be DISKEW ) is the CISKEW Freescale Semiconductor Unit V V Unit ...

Page 23

... MCS[n] output setup with respect to MCK MCS[n] output hold with respect to MCK MCK to MDQS Skew MDQ/MECC/MDM output setup with respect to MDQS MDQ/MECC/MDM output hold with respect to MDQS MDQS preamble start MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 1 Symbol Min t 3.75 MCK t DDKHAS 533 MHz 1 ...

Page 24

... DDR timing (DD) for the time t DDKLDX NOTE t MCK t = 0.6 ns DDKHMHmax –0.6 ns DDKHMH(min) Figure 3. Timing Diagram for tDDKHMH Max Unit Notes 0.6 ns memory clock reference MCK describes the DDR timing (DD) DDKHMH can be modified through control DDKHMH follows the DDKHMP Table 19 DDKHMH Freescale Semiconductor 6 for ). ...

Page 25

... DDR SDRAM output timing diagram.+ MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 4. DDR SDRAM Output Timing Diagram Figure 5 provides the AC test load for the DDR bus. Output MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor t MCK DDKHAS DDKHCS DDKHAX DDKHCX NOOP ...

Page 26

... Subsequent bit values are Min Max 0.3 DD –0.3 0.8 IL — ±5 2.4 — — 0.4 Table 1 and Table 2. Value Unit f /1,048,576 baud CCB f /16 baud CCB 16 — Freescale Semiconductor Unit V V  Notes ...

Page 27

... supports eTSECs 3 and The symbol this case, represents the LV IN MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor and Table 23. The RGMII and RTBI signals are based on a 2.5-V CMOS Symbol Min LV 3.13 DD ...

Page 28

... Min LV / GND–0 1. –0 — –15 IL and TV symbols referenced Max Unit Notes 2. /TV + 0.3 V — 0.40 V — LV /TV + 0.3 V — 0.90 V —  A — 3 Table 1 and Table 2. Freescale Semiconductor ...

Page 29

... The minimum cycle period of the TX_CLK and RX_CLK is dependent on the maximum platform frequency speed bins the part belongs to as well as the FIFO mode under operation. See Timing diagrams for FIFO appear in GTX_CLK t FITH TXD[7:0] TX_EN TX_ER MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Table 24 Symbol t t FITH t t FITR t ...

Page 30

... GMII transmit timing (GT) with respect to the t GTKHDX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention t FIRR t FIRF Min Typ Max Unit 2.5 — — 0.5 — 5.0 — — 1.0 — — 1.0 for inputs symbolizes GMII transmit timing GTKHDV GTX Freescale Semiconductor clock ...

Page 31

... For example, the subscript of t GRX is used with the appropriate letter: R (rise (fall). 2. Guaranteed by design. Figure 9 provides the AC test load for eTSEC. Output MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor t GTX t t GTXH GTXF t GTKHDX ...

Page 32

... For example, t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is t GRXR Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 symbolizes MII transmit MTKHDX Freescale Semiconductor Unit for ...

Page 33

... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used MRX with the appropriate letter: R (rise (fall). 2. Guaranteed by design. Figure 12 provides the AC test load for eTSEC. Output MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor t MTX t t MTXF MTXH t MTKHDX Figure 11 ...

Page 34

... TTX symbolizes the TBI transmit timing (TT) with respect to the time from t t MRXR t MRDXKL Min Typ Max 2.0 — — 1.0 — — — — 1.0 — — 1.0 symbolizes the TBI TTKHDV (K) going high TTX Freescale Semiconductor Unit for ...

Page 35

... TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the TRX appropriate letter: R (rise (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor t TTX t TTXH t ...

Page 36

... Figure 15. TBI Receive AC Timing Diagram Symbol t TRRX t TRRH/TRRX t TRRJ t TRRR t TRRF t TRRDVKH t TRRDXKH t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Table 32. Min Typ Max 7.5 8.0 8 — — 250 — — 1.0 — — 1.0 2.0 — — 1.0 — — Freescale Semiconductor Unit ...

Page 37

... Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t between. 5. Guaranteed by characterization rev 1.0 silicon, due to errata, t SKRGT MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Figure 16. t TRRX Valid Data t ...

Page 38

... RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR 1 Symbol t RMT t RMTH t RMTJ t RMTR t RMTF t RGT t SKRGT t SKRGT Min Typ Max Unit 15.0 20.0 25 — — 250 1.0 — 2.0 1.0 — 2.0 Freescale Semiconductor ...

Page 39

... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used MRX with the appropriate letter: R (rise (fall). MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 1 Symbol t RMTDX (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

Page 40

... RMII receive AC timing diagram. TSECn_TX_CLK RXD[1:0] CRS_DV RX_ER MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev  Figure 19. eTSEC AC Test Load t RMR t t RMRF RMRH Valid Data t RMRDV Figure 20. RMII Receive AC Timing Diagram  RMRR t RMRDX Freescale Semiconductor ...

Page 41

... MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics “Section 8, “Enhanced Three-Speed Ethernet Symbol –1.0 mA) ...

Page 42

... MDCH MDCF t MDDVKH t MDDXKH t MDKHDX Typ Max Unit 10 ns symbolizes management MDKHDX CCB = 533)  (2 × 4 × 533)  MDC ), the ECn_MDC output clock frequency can be CCB  448. See 14.5.3.6.6, “MII Management CCB t MDCR Freescale Semiconductor Notes 4 for ). The actual ...

Page 43

... High-level output voltage (BV = min Low-level output voltage (BV = min Note: 1. Note that the symbol this case, represents the BV IN MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Symbol –2 mA 2mA) ...

Page 44

... LBIXKH1 clock reference (K) goes high (H), in this case clock reference ( high (H), with respect LBOTOT Freescale Semiconductor Notes 2 — — for is ...

Page 45

... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals Guaranteed by design. Figure 22 provides the AC test load for the local bus. Output MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor DD Symbol t LBKH/ t LBKSKEW t LBIVKH1 ...

Page 46

... LBKHOX2 t LBOTOT t LBKHOV4 Figure 23. Local Bus Signals (PLL Enabled) Symbol t LBKH/ t LBIXKH1 t LBIXKH2 = 3.3 V with PLL disabled Min Max Unit t 12 — ns LBK LBK t 2.3 4.4 ns LBKHKT t 6.2 — ns LBIVKH1 t 6.1 — ns LBIVKL2 t –1.8 — ns LBIXKH1 Freescale Semiconductor Notes 2 — ...

Page 47

... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Guaranteed by characterization. 9. Guaranteed by design. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Symbol t LBIXKL2 t ...

Page 48

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHKT t LBKLOV1 t LBKLOV2 t LBKLOV3 t LBKLOV4 NOTE . In this mode, signals are launched at the rising edge t LBKHKT t LBIVKH1 t LBIXKH1 t LBIVKL2 t LBIXKL2 t t LBKLOX1 t t LBKLOX2 t LBOTOT Freescale Semiconductor LBKLOZ1 LBKLOZ2 ...

Page 49

... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor t t LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 ...

Page 50

... Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKLOX1 LBKLOV1 t LBIVKH1 t LBKLOZ1 t LBIVKL2 t LBIXKL2 t LBIXKH1 Freescale Semiconductor ...

Page 51

... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor t t LBKHOV1 LBKHOZ1 t LBIVKH2 t ...

Page 52

... Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKLOX1 LBKLOV1 t LBIVKH1 t LBKLOZ1 t LBIVKL2 t LBIXKL2 t LBIXKH1 Freescale Semiconductor ...

Page 53

... JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Input hold times: MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 1 Symbol ...

Page 54

... VM = Midpoint Voltage (OV DD /2) 1 (continued) Min Max Unit — 30 — the midpoint of the signal in question. TCLK Figure symbolizes JTAG device JTDVKH clock reference (K) JTG  JTGR t JTGF Freescale Semiconductor Notes 29). for ...

Page 55

... JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor VM t TRST VM = Midpoint Voltage (OV DD /2) Figure 31. TRST Timing Diagram VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 32 ...

Page 56

... Min Max Unit 0 400 kHz s 1.3 — s 0.6 — s 0.6 — s 0.6 — 100 — ns s — — 0 — — 0.9 — s 0.6 — s 1.3 — Freescale Semiconductor Notes — — — Notes — — — ...

Page 57

... The maximum t has only to be met if the device does not stretch the LOW period (t I2DXKL 4. Guaranteed by design. Figure 33 provides the AC test load for the I Output MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Electrical Specifications (continued) 1 Symbol 0.1  0.2  ...

Page 58

... AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev bus I2DVKH I2KHKL t I2SXKL t t I2CH I2SVKH t t I2DXKL, I2OVKL Sr 2 Figure 34 Bus AC Timing Diagram t I2CF t I2CR t I2PVKH P S Freescale Semiconductor ...

Page 59

... High-level input voltage Low-level input voltage Input current 1 ( Note: 1. The symbol this case, represents the BV IN MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor DC Electrical Characteristics (3.3 V DC) OUT Symbol Min BV 3. – 0 — ...

Page 60

... IN Symbol – symbol referenced in IN Max Unit 2. 0 0.7 V A 10 Table 1. 1 Min Max Unit 0 –0.3 0.8 V A — ±5 2.4 — V — 0.4 V Table 1 and Table 2. Freescale Semiconductor Notes — — 2 — — ...

Page 61

... PCI 2.2 Local Bus PCRHFV Specifications. 9. The reset assertion timing requirement for HRESET is 100 s. 10.Guaranteed by characterization. 11.Guaranteed by design. Figure 35 provides the AC test load for PCI and PCI-X. Output MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 1 Symbol t PCKHOV t PCKHOX t PCKHOZ t ...

Page 62

... Symbol t PCKHOV t PCKHOX t PCKHOZ t PCIVKH t PCIXKH t PCRVRH t PCRHRX t PCRHFV t PCIVRH t PCIXKH Min Max Unit Notes — 3 0.7 — — 1.7 — 0.5 — — clocks — clocks — clocks 11 Freescale Semiconductor ...

Page 63

... Input setup time to SYSCLK Input hold time from SYSCLK REQ64 to HRESET setup time HRESET to REQ64 hold time HRESET high to first FRAME assertion PCI-X initialization pattern to HRESET setup time MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Symbol Min Max ...

Page 64

... PCI-X 1.0a PCRHFV Specification. 11.Guaranteed by characterization. 12.Guaranteed by design. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min Max PCRHIX and t only in PCI-X mode. In conventional PCKHOV CYC Freescale Semiconductor Unit Notes PCRHFV ...

Page 65

... V • Common mode voltage, V The common mode voltage is equal to one half of the sum of the voltages between each conductor MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor (or differential output swing): OD – V SD_TX SD_TX ...

Page 66

... V ID Differential Peak Voltage, V Differential Peak-Peak Voltage, V DIFFpp is 500 mV in one phase and –500 mV in the other phase. The peak OD are specified in DD_SRDS2 cm_out B)/ – – B| DIFFp = 2*V (not shown) DIFFp ) is 1000 mVp-p. DIFFp-p Table 1 and Table 2. Freescale Semiconductor = ) OD ...

Page 67

... The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below: • Differential mode MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) 50  Input Amp 50  ...

Page 68

... Section 16.2.1, “SerDes Reference Clock the maximum average current requirements sets the requirement for Figure 41 shows the SerDes reference clock Figure 40 shows the with min max Figure 42 shows V < 800 mV max 100 mV < V < 400 > min Freescale Semiconductor ...

Page 69

... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

Page 70

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev SD_REF_CLK 100 Differential PWB Trace SD_REF_CLK Clock driver vendor dependent source termination resistor SD_REF_CLK 100 Differential PWB Trace SD_REF_CLK MPC8548E 50  SerDes Refer. CLK Receiver 50  MPC8548E 50  SerDes Refer. CLK Receiver 50  Figure 45 assumes that Freescale Semiconductor ...

Page 71

... It assumes the DC levels of the clock driver are compatible with the SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip 33  Clock Driver CLK_Out Figure 46. Single-Ended Connection (Reference Only) MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor SD_REF_CLK 100 Differential PWB Trace SD_REF_CLK Total 50  ...

Page 72

... Note that external an AC coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in the specification of each protocol section. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev SD_TXn SD_RXn SD_TXn SD_RXn 50  Receiver 50  Freescale Semiconductor ...

Page 73

... Specification. Rev. 1.0a. 17.4.1 Differential Transmitter (TX) Output Table 56 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor PCI Express Min Typ Max Unit Notes — ...

Page 74

... V) in relation TX-DIFFp-p = RMS(| |/2 – TXD+ TXD– |/2. (avg) TX-D+ TX-D– TX-CM-Idle-DC (during |  100 |/2 [L0] (avg) TX-D+ TX-D– |/2 (avg) TX-D+ TX-D– |  – V TX-CM-DC-D– (avg) TX- (avg) TX-D– – TX-IDLE-D+ TX-IDLE-D– Freescale Semiconductor ...

Page 75

... TX-DIFF-DC TX impedance Z Transmitter DC TX-DC impedance L Lane-to-lane TX-SKEW output skew C AC coupling TX capacitor MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Min Nom Max Unit 0 — 3.6 V The allowed DC common mode voltage under any conditions. See Note 6. — — The total current the transmitter can provide when ...

Page 76

... See Note 7. TX-EYE-MEDIAN-to-MAX-JITTER is specified using the passive compliance/test measurement load (see NOTE Comments Figure 50 and measured over Figure 48.) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 50). Note that the series capacitors Figure 50 for both V and V TX-D+ TX-D– Freescale Semiconductor . ...

Page 77

... Maximum time RX-EYE-MEDIAN-to- between the MAX-JITTER jitter median and maximum deviation from the median MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor [Transition Bit 800 mV TX-DIFFp-p-MIN [De-Emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0. – 0 ...

Page 78

... Measured at the package pins of the receiver — — unexpected electrical idle (V V RX-IDLE-DET-DIFFp-p longer than T an unexpected idle condition. Comments = |V – RXD+ RXD- RX-CM-DC |  (avg) RX-D+ RX-D– × |V –V |. RX-D+ RX-D– < RX-DIFFp-p ) must be recognized no to signal RX-IDLE-DET-DIFF-ENTERING Freescale Semiconductor ...

Page 79

... RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Min Nom Max Unit — ...

Page 80

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE Figure 50). Note that the series capacitors, CTX, are V > 175 mV RX-DIFFp-p-MIN 0 RX-EYE-MIN NOTE Pin Pin Silicon + Package  Pin RX-DIFF (D+ D– Crossing Point) Figure 50  Freescale Semiconductor ...

Page 81

... REFCLK cycle-to-cycle jitter. Difference in the REFCJ period of any two adjacent REFCLK cycles. t Phase jitter. Deviation in edge location with REFPJ respect to mean edge location. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Min Typ Max Unit — 10(8) — applies only to serial ...

Page 82

... The use of active circuits in the receiver. This is often referred to as adaptive equalization. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Figure 51 shows how the signals are defined. The figures show , is defined defined Differential Peak-to-Peak = 2  (A – B) – – Freescale Semiconductor ...

Page 83

... Differential output voltage V DIFFPP Deterministic jitter J D Total jitter J T Multiple output skew S MO Unit Interval UI MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Range Unit Min Max –0.40 2.30 V Voltage relative to COMMON of either signal comprising a differential pair 500 1000 mV p-p — 0.17 UI p-p — ...

Page 84

... Voltage relative to COMMON of either signal comprising a differential pair 800 1600 mVp-p — 0.17 UI p-p — 0.35 UI p-p — 1000 ps Skew at the transmitter output between lanes of a multilane link 800 800 ps ±100 ppm Notes — — — Notes — — — Notes — — — Freescale Semiconductor ...

Page 85

... Figure 52 with the parameters specified in the device is driving a 100- ± 5% differential resistive load. The output eye pattern of an LP-serial MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Range Unit Min Max –0.40 2 ...

Page 86

... AC coupling MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Time min (mV) V max (mV) DIFF DIFF 250 500 400 800 250 500 400 800 250 500 400 800 1-B 1-A A (UI) B (UI) 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 Freescale Semiconductor 1 ...

Page 87

... Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Range Symbol Unit ...

Page 88

... T S — -12 BER — 320 320 ps Frequency Notes Measured at receiver Measured at receiver Measured at receiver Measured at receiver Skew at the receiver input between lanes of a multilane link — ±100 ppm Figure 53. The sinusoidal jitter component 1.875 MHz 20 MHz Freescale Semiconductor ...

Page 89

... Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly guided by Clause 47. Additionally, the CJPAT test pattern defined in Annex 48A of IEEE Std. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor (Table 66, Table ...

Page 90

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Figure 54 and Table 69. Note that for this to occur, the test signal must Section 18.7, “Receiver Specifications,” Continuous Jit Section 18.7, “Receiver Specifications,” Freescale Semiconductor –12 . ter test is ...

Page 91

... Solder ball (lead-free) Notes: 1. The HiCTE FC-CBGA package is available on only Version 2.0 of the device. 2. The FC-PBGA package is available on only versions 2.1.1 and 2.1.2, and 3.0 of the device. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Table 70. Package Parameters 1 CBGA 29 mm  783 ...

Page 92

... The following figures show the mechanical dimensions and bottom surface nomenclature for the MPC8548E HiCTE FC-CBGA and FC-PBGA packages. Figure 55. Mechanical Dimensions and Bottom Surface Nomenclature of the HiCTE FC-CBGA and FC-PBGA with Full Lid MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 93

... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. 6. All dimensions are symmetric across the package center lines unless dimensioned otherwise. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Description 93 ...

Page 94

... Parallelism measurement shall exclude any effect of mark on top surface of package. 8. All dimensions are symmetric across the package center lines unless dimensioned otherwise. Figure 56. Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA with Stamped Lid MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 95

... PCI1_PAR PCI1_PERR PCI1_SERR PCI1_STOP PCI1_TRDY MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor NOTE Table 71. MPC8548E Pinout Listing Package Pin Number PCI1 and PCI2 (One 64-Bit or Two 32-Bit) AB14, AC15, AA15, Y16, W16, AB16, AC16, AA16, AE17, AA18, W18, AC17, AD16, AE16, ...

Page 96

... I OV — I/O OV — — DD I/O OV — DD I/O GV — DD I/O GV — — DD I/O GV — DD I/O GV — — — DD Freescale Semiconductor ...

Page 97

... LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0:2] MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number F10, C10, J11, H11 K8, J8, G8, F8 H9, B15, G2, M9, A14, F1 J9, A15, G1, L9, B14, F2 E6, K6, L7, M7 A19, B19 ...

Page 98

... I OV — I I I/O OV — — — — — — — — — — DD Freescale Semiconductor ...

Page 99

... Three-Speed Ethernet Controller (Gigabit Ethernet 4) TSEC4_TXD[3:0]/TSEC3_TXD[7:4] TSEC4_RXD[3:0]/TSEC3_RXD[7:4] TSEC4_GTX_CLK TSEC4_RX_CLK/TSEC3_COL TSEC4_RX_DV/TSEC3_CRS TSEC4_TX_EN/TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number P2, R2, N1, N2, P3, M2, M1, N3 N9, N10, P8, N7, R9, N5, R8 P10 P7 ...

Page 100

... — — 2 — — 32 — — 34 — — — — — — — 19 19 Freescale Semiconductor ...

Page 101

... TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP GND OV DD MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number Clock AF16 AH17 JTAG AG28 AH28 AF28 AH27 AH23 DFT AC25 AE22 AH20 AH14 ...

Page 102

... V) Pad Power for XV — DD SerDes transceivers (1.1 V) Power for local — 26 bus PLL (1.1 V) Power for — 26 PCI1 PLL (1.1 V) Power for — 26 PCI2 PLL (1.1 V) Power for — 26 e500 PLL (1.1 V) Power for CCB — 26 PLL (1.1 V) Power for — 26 SRDSPLL (1 Freescale Semiconductor ...

Page 103

... FIFO mode when used as Rx flow control. 24.Do not connect. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number M16 Analog Signals A18 ...

Page 104

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 104 Package Pin Number . through 2–10 k resistors if they are not used. DD through 2–10 k resistors. DD through 2–10 k resistors. DD Power Pin Type Notes Supply for normal machine operation through an 18.2- precision DD ) through DD ) through DD Freescale Semiconductor ...

Page 105

... PCI1_IDSEL PCI1_REQ64 PCI1_ACK64 Reserved Reserved Reserved MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor NOTE for the meanings of these notes. Table 72. MPC8547E Pinout Listing Package Pin Number PCI1 (One 64-Bit or One 32-Bit) AB14, AC15, AA15, Y16, W16, AB16, AC16, ...

Page 106

... I/O GV — DD I/O GV — — DD I/O GV — DD I/O GV — — — — — — — — — — Freescale Semiconductor ...

Page 107

... DMA_DREQ[0:1] DMA_DDONE[0:1] UDE MCP MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number Local Bus Controller Interface E27, B20, H19, F25, A20, C19, E28, J23, A25, K22, B28, D27, D19, J22, K20, D28, D25, B25, E22, F22, F21, C25, C22, B23, F20, A23, A22, ...

Page 108

... I LV — — — — — — — — — — — — — — Freescale Semiconductor ...

Page 109

... UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD_RX[0:3] SD_RX[0:3] SD_TX[0:3] SD_TX[0:3] Reserved Reserved MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number R10 V8, W10, Y10, W7 Y1, W3, W5 V10 V9 AB8, Y7, AA7, Y8 AA1, Y3, AA2, AA4 AA5 Y5 ...

Page 110

... — — — 19 19 — — — — Freescale Semiconductor ...

Page 111

... THERM0 THERM1 ASLEEP GND MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number DFT AC25 AE22 AH20 AH14 Thermal Management AG1 AH1 Power Management AH18 Power and Ground Signals A11, B7, B24, C1, C3, C5, C12, C15, C26, D8, ...

Page 112

... PCI2 PLL (1.1 V) Power for — 26 e500 PLL (1.1 V) Power for CCB — 26 PLL (1.1 V) Power for — 26 SRDSPLL (1 — — MVREF — Reference voltage signal for DDR 200  — GND 100  — GND Freescale Semiconductor ...

Page 113

... PCI1_SERR PCI1_STOP PCI1_TRDY PCI1_REQ[4:1] PCI1_REQ0 PCI1_CLK PCI1_DEVSEL MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number U26 Table NOTE for the meanings of these notes. Table 73. MPC8545E Pinout Listing Package Pin Number PCI1 and PCI2 (One 64-Bit or Two 32-Bit) ...

Page 114

... DD I/O OV 2 — DD I/O OV — DD I/O GV — DD I/O GV — — DD I/O GV — DD I/O GV — — — — — — — — — — DD Freescale Semiconductor ...

Page 115

... LSYNC_OUT DMA_DACK[0:1] DMA_DREQ[0:1] DMA_DDONE[0:1] MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number A19, B19 Local Bus Controller Interface E27, B20, H19, F25, A20, C19, E28, J23, A25, K22, B28, D27, D19, J22, K20, D28, D25, B25, ...

Page 116

... — — — — — — — 103 — — DD — — 104 — — 104 — — 15 — — 105 Freescale Semiconductor ...

Page 117

... Reserved TSEC3_COL TSEC3_CRS TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD_RX[0:3] SD_RX[0:3] SD_TX[0:3] MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number P5 R1 P10 P7 R10 V8, W10, Y10, W7 Y1, W3, W5 V10 V9 AB8, Y7, AA7, Y8 AA1, Y3, AA2, AA4 ...

Page 118

... O BV — — — — — 19 19 — — — Freescale Semiconductor ...

Page 119

... L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP GND MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number AF28 AH27 AH23 DFT AC25 AE22 AH20 AH14 Thermal Management AG1 AH1 Power Management AH18 Power and Ground Signals ...

Page 120

... PLL (1.1 V) Power for — 26 PCI1 PLL (1.1 V) Power for — 26 PCI2 PLL (1.1 V) Power for — 26 e500 PLL (1.1 V) Power for CCB — 26 PLL (1.1 V) Power for — 26 SRDSPLL (1 — — MVREF — Reference voltage signal for DDR Freescale Semiconductor ...

Page 121

... PCI1_C_BE[3:0] Reserved PCI1_GNT[4:1] PCI1_GNT0 PCI1_IRDY PCI1_PAR PCI1_PERR PCI1_SERR PCI1_STOP MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number L28 AB26 U26 NOTE for the meanings of these notes. Table 74. MPC8543E Pinout Listing Package Pin Number PCI1 (One 32-Bit) ...

Page 122

... — — 101 — — 110 — — 110 — — 110 — — 110 — — 110 — — 110 — — 110 I/O GV — DD I/O GV — — DD I/O GV — DD I/O GV — — — DD Freescale Semiconductor ...

Page 123

... LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0:2] MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number F10, C10, J11, H11 K8, J8, G8, F8 H9, B15, G2, M9, A14, F1 J9, A15, G1, L9, B14, F2 E6, K6, L7, M7 A19, B19 ...

Page 124

... I I I/O OV — — — — — — — — — — 103 DD Freescale Semiconductor ...

Page 125

... TSEC3_RX_DV TSEC3_RX_ER TSEC3_TX_CLK TSEC3_TX_EN TSEC3_TXD[7:4] TSEC3_RXD[7:4] Reserved TSEC3_COL TSEC3_CRS TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] IIC1_SCL MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number N9, N10, P8, N7, R9 P10 P7 R10 V8, W10, Y10, W7 Y1, W3, W5, W4 ...

Page 126

... O BV — — — — — 19 19 — — DD Freescale Semiconductor ...

Page 127

... Y11, Y19, AA6, AA14, AA17, AA22, AA23, AB4, U24, V25, W28, Y24, Y26, AA24, AA27, AB25, AC28, L21, L23, N22, P20, R23, T21, U22, V20 MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number JTAG AG28 AH28 AF28 AH27 AH23 ...

Page 128

... V) Pad power XV — DD for SerDes transceivers (1.1 V) Power for — 26 local bus PLL (1.1 V) Power for — 26 PCI1 PLL (1.1 V) Power for — 26 PCI2 PLL (1.1 V) Power for — 26 e500 PLL (1.1 V) Power for — 26 CCB PLL (1.1 V) Power for — 26 SRDSPLL (1 Freescale Semiconductor ...

Page 129

... Signal SENSEVSS MVREF SD_IMP_CAL_RX SD_IMP_CAL_TX SD_PLL_TPA Note: All note references in this table use the same numbers as those for notes. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Package Pin Number M16 Analog Signals A18 L28 AB26 U26 Table 71. See ...

Page 130

... Max Min Max Min 800 800 800 1000 800 and Section 20.3, “e500 Core PLL Ratio,” Table 78, 1333 MHz Unit Notes Max 1333 MHz 1, 2 for ratio settings. 1200 MHz Unit Notes Max 1200 MHz 1, 2 for ratio settings. Freescale Semiconductor ...

Page 131

... See Section 20.2, “CCB/SYSCLK PLL Ratio,” settings. 2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Maximum Processor Core Frequency 800 MHz 1000 MHz Min ...

Page 132

... Maximum Processor Core Frequency 800, 1000 MHz Min 166 and Section 20.3, “e500 Core PLL Ratio,” Table 81. CCB Clock Ratio 16:1 1000 Reserved 1001 2:1 1010 3:1 1011 4:1 1100 5:1 1101 6:1 1110 Reserved 1111 Unit Notes Max 200 MHz 1, 2 for ratio Table 81: 8:1 9:1 10:1 Reserved 12:1 20:1 Reserved Reserved Freescale Semiconductor ...

Page 133

... Note: Due to errata Gen 13 the max sys clk frequency must not exceed 100 MHz if the core clk frequency is below 1200 MHz. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Table 82. e500 Core to CCB Clock Ratio Binary Value of LBCTL, LALE, LGPL2 ...

Page 134

... Single-layer board (1s) R  JA Four-layer board (2s2p) R  JA Single-layer board (1s) R  JA Four-layer board (2s2p) R  JA Value Unit Notes 17 °C °C °C °C °C/W 3 0.8 °C/W 4 Value Unit Notes 18 °C °C °C °C Freescale Semiconductor ...

Page 135

... Each of the PLLs listed above is provided with power through independent power supply pins (AV _PLAT, AV _CORE MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor JEDEC Board N/A N/A Section 20.2, “CCB/SYSCLK PLL Ratio.” Section 20.3, “e500 Core PLL Ratio.” _PCI, AV _LBIU, and AV ...

Page 136

... Low ESL Surface Mount Capacitors GND 10 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 57, one to each of the pin being supplied to minimize noise DD pin, which _PLAT DD AV _CORE DD AV _PCI/AV _LBIU DD DD _SRDS to DD Freescale Semiconductor DD ...

Page 137

... An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors must be used to minimize inductance. Connections from all capacitors to power and ground must be done with multiple vias to further reduce inductance. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 1 1 2.2 µF 2.2 µF GND Figure 60 ...

Page 138

... MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 138 , C). is trimmed until the voltage at the pad equals P P )/2. N and and (see Figure 61). The DD and R are designed to be close to each N Freescale Semiconductor ) ...

Page 139

... Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor minimizes the disruption of signal quality or speed for output pins thus configured. MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Pad ...

Page 140

... Freescale recommends that the COP header be designed into the system MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 140 allows the COP port to independently assert HRESET or TRST, Figure 62, for connection to the target system, and is Figure 62 is common to Freescale Semiconductor ...

Page 141

... If this is not possible, the isolation resistor allows future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. • No pull-up/pull-down is required for TDI, TMS, TDO, or TCK. COP_RUN/STOP COP_CHKSTP_OUT MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 2 COP_TDO 1 1 COP_TDI 3 ...

Page 142

... COP_VDD_SENSE NC COP_CHKSTP_OUT 10 k COP_CHKSTP_IN COP_TMS COP_TDO COP_TDI COP_TCK Figure 63. JTAG Interface Connection k 6 SRESET 1 10 k HRESET 10 k 10 k 10 k 10 k 1 TRST CKSTP_OUT 10 k CKSTP_IN TMS TDO TDI TCK Freescale Semiconductor ...

Page 143

... Reserved pins: T22, T23, M20, M21 The following pins must be connected to GND if not used: • SD_RX[7:0] • SD_RX[7:0] • SD_REF_CLK MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor NOTE . Pins V27 and M25 must be tied to GND through a 300- DD System Design Information 143 ...

Page 144

... For LPBSE—tie it to the power supply rail via a 4.7-k resistor (pull-up resistor). MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 144 NOTE . Pins V27 and M25 must be tied to GND through a 300- through a single 10-k resistor. through a single 10-k resistor. Freescale Semiconductor ...

Page 145

... Part Temperature Code Identifier MPC 8548E Blank = 0 to 105 –40 to 105C 8548 8547E 8547 MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Table 87. Part Numbering Nomenclature pp Processor Package Frequency HX = CBGA AV = 1500 VU = Pb-free CBGA AU = 1333 PX = PBGA ...

Page 146

... Silicon Version 4 Frequency G = 400 Blank = Ver. 2.0 (SVR = 0x80390220 Ver. 2.1 Ver. 2.1 Ver. 3.1.x (SVR = 0x80390231) Blank = Ver. 2.0 (SVR = 0x80310220 Ver. 2.1 Ver. 2.1 Ver. 3.1.x (SVR = 0x80310231) Blank = Ver. 2.0 (SVR = 0x803A0020 Ver. 2.1 Ver. 2.1 Ver. 3.1.x (SVR = 0x803A0031) Blank = Ver. 2.0 (SVR = 0x80320020 Ver. 2.1 Ver. 2.1 Ver. 3.1.x (SVR = 0x80320031) Freescale Semiconductor ...

Page 147

... MMMMM is 5 digit mask number. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. YWWLAZ is assembly traceability code. Figure 64. Part Marking for CBGA and PBGA Device MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Figure 64. (F) MPC8548xxxxxx ...

Page 148

... Rate” added explanation that Power-On Ramp Rate is required to Table 37, “MII Management AC Timing Specifications.” “MII Management AC Timing Specifications.” Rate.” Rate”. to include Thermal Version 2.1.3 and Version 3.1.x Parameters” with Version 3.1.x silicon information. Table 44, “JTAG AC Timing 72, “MPC8547E Pinout Listing,” Table Freescale Semiconductor 73, ...

Page 149

... Added information to • Section 22.3, “Decoupling Recommendations.” • Table 87, “Part Numbering Nomenclature.” MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor Substantive Change(s) 1 ,” and in DD Table 75, “Processor Core Clocking Specifications (MPC8548E and MPC8547E), “.” “Differential Transmitter (TX) Output Specifications,” modified equations in Comments 83, “ ...

Page 150

... Table 40, “Local Bus LBIXKH1 LBIXKH2 Table 40, “Local Bus Timing Parameters , t , and t in Table 42, “Local Bus LBIXKH1 LBIXKL2 and t were previously labeled t LBIXKL2 Enabled)” and Figure 24, “Local Bus and Figure 28. 28. Specifications” Lid.” Freescale Semiconductor Table 32, LBIVKH2 ...

Page 151

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