552BC000206DG Silicon Labs, 552BC000206DG Datasheet

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552BC000206DG

Manufacturer Part Number
552BC000206DG
Description
VCXO Oscillators DUAL VCXO 6 PIN 7mm x 5mm
Manufacturer
Silicon Labs
Datasheet

Specifications of 552BC000206DG

Product Category
VCXO Oscillators
Rohs
yes
Package / Case
7 mm x 5 mm
Frequency
245.76 MHz
Frequency Stability
50 PPM
Supply Voltage
3.3 V
Termination Style
SMD/SMT
Dimensions
5 mm W x 7 mm L x 1.65 mm H
Minimum Operating Temperature
- 40 C
Maximum Operating Temperature
+ 85 C
Mounting Style
Solder Pad
Product
VCXO
Supply Voltage - Max
3.63 V
Supply Voltage - Min
2.97 V
D
O
Features
Applications
Description
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments typically found in communication
systems. The Si552 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
Rev. 1.0 1/12
Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL
jitter performance
3x better frequency stability than
SAW-based oscillators
SONET/SDH
xDSL
10 GbE LAN/WAN
U A L
SCILLATOR
®
circuitry to provide a very low jitter clock for all output frequencies.
F
REQUENCY
V
V
Frequency XO
DD
C
Fixed
ADC
®
( V C X O ) 1 0 MH
with superior
Clock Synthesis
10–1400 MHz
Any-rate
DSPLL
FS
Copyright © 2012 by Silicon Laboratories
V
®
OLTAGE
Low-jitter clock generation
Optical modules
Clock and data recovery
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
CLK-
GND
CLK+
- C
Z TO
ON TROLLED
1.4 G H
Ordering Information:
Z
GND
C
Pin Assignments:
FS
V
C
R Y S TA L
See page 9.
See page 8.
Si5602
(Top View)
1
2
3
R
Si 552
E V I S I O N
6
5
4
V
CLK–
CLK+
DD
Si552
D

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552BC000206DG Summary of contents

Page 1

REQUENCY SCILLATOR Features  Available with any-rate output frequencies from 10–945 MHz and selected frequencies to 1.4 GHz  Two selectable output frequencies ®  ...

Page 2

Si 552 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current 2 Frequency Select (FS) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 9 for ...

Page 3

Table 3. CLK± Output Frequency Characteristics Parameter Symbol 1,2,3 Nominal Frequency 1,4 Temperature Stability 1,4 Absolute Pull Range Aging 5 Power up Time Settling Time After FS Change Notes: 1. See Section 3. "Ordering Information" on page 9 for further ...

Page 4

Si 552 Table 5. CLK± Output Phase Jitter Parameter Symbol 1,2,3 Phase Jitter (RMS) for F > 500 MHz OUT Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always ...

Page 5

Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol 1,2,3,4,5 Phase Jitter (RMS) for F of 125 to 500 MHz OUT Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, ...

Page 6

Si 552 Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol 1,2,5 Phase Jitter (RMS) for 160 MHz OUT CMOS Output Only Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter ...

Page 7

Table 7. CLK± Output Phase Noise (Typical) Offset Frequency 74.25 MHz 90 ppm/V LVPECL 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Table 8. Environmental Compliance The Si552 meets the following qualification test requirements. ...

Page 8

Si 552 2. Pin Descriptions Pin Name FS* 3 GND 4 CLK+ CLK– 5 (N/A for CMOS *Note: FS includes a 17 k pullup resistor to V select and OE polarity ordering options. ...

Page 9

... Specific device configurations are programmed into the Si552 at time of shipment. Configurations are DD specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. Refer to and for further ordering instructions. The Si552 VCXO series is supplied in an industry-standard, RoHS-compliant, lead-free, 6-pad package ...

Page 10

Si 552 4. Package Outline and Suggested Pad Layout Figure 2 illustrates the package details for the Si552. Table 11 lists the values for the dimensions shown in the illustration. Table 11. Package Diagram Dimensions (mm) Dimension ...

Page 11

PCB Land Pattern Figure 3 illustrates the 6-pin PCB land pattern for the Si552. Table 12 lists the values for the dimensions shown in the illustration. Table 12. PCB Land Pattern Dimensions (mm) Dimension ...

Page 12

Si 552 6. Top Marking 6.1. Si552 Top Marking   6.2. Top Marking Explanation Line Position 1 1–10 “SiLabs”+ Part Family Number, 552 (First 3 characters in part number) 2 1–10 Si552: Option1+Option2+Freq(7)+Temp Si552 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp 3 Trace ...

Page 13

OCUMENT HANGE IST Revision 0.6 to Revision 1.0  Updated Table 4 on page 3. Updated 2.5 V/3.3 V and 1.8 V CML output level  specifications.  Updated Table 5 on page 4. Removed the words ...

Page 14

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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