550CK24M5760DG Silicon Labs, 550CK24M5760DG Datasheet
550CK24M5760DG
Specifications of 550CK24M5760DG
Related parts for 550CK24M5760DG
550CK24M5760DG Summary of contents
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TAG E ONTR OLLED Features Available with any frequency from 10 to 945 MHz and select frequencies to 1.4 GHz ® 3rd generation DSPLL with superior ...
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Si 550 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current 2 Output Enable (OE) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 9 for further ...
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Table 3. CLK± Output Frequency Characteristics Parameter Symbol 1,2,3 f Nominal Frequency O 1,4 Temperature Stability 1,4 Absolute Pull Range APR Aging 5 Power up Time t OSC Notes: 1. See Section 3. "Ordering Information" on page 9 for further ...
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Si 550 Table 5. CLK± Output Phase Jitter Parameter Symbol 1,2,3 Phase Jitter (RMS) for F > 500 MHz OUT Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always ...
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Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol 1,2,3,4,5 Phase Jitter (RMS) for F of 125 to 500 MHz OUT Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, ...
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Si 550 Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol 1,2,5 Phase Jitter (RMS) for 160 MHz OUT CMOS Output Only Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter ...
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Table 7. CLK± Output Phase Noise (Typical) Offset Frequency 74.25 MHz 90 ppm/V LVPECL 100 Hz –87 1 kHz –114 10 kHz –132 100 kHz –142 1 MHz –148 10 MHz –150 100 MHz n/a Table 8. Environmental Compliance The ...
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Si 550 2. Pin Descriptions Pin Name OE* 3 GND 4 CLK+ CLK– 5 (N/A for CMOS *Note: OE includes 17 k pullup resistor to V ordering options. 8 (Top View ...
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... Specific device configurations are programmed into the Si550 at time of shipment. Configurations are DD specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. Refer to and for further ordering instructions. The Si550 VCXO series is available in an industry-standard, RoHS compliant, lead-free, 6-pad package ...
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Si 550 4. Package Outline and Suggested Pad Layout Figure 2 illustrates the package details for the Si550. Table 11 lists the values for the dimensions shown in the illustration. Table 11. Package Diagram Dimensions (mm) Dimension ...
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PCB Land Pattern Figure 3 illustrates the 6-pin PCB land pattern for the Si550. Table 12 lists the values for the dimensions shown in the illustration. Table 12. PCB Land Pattern Dimensions (mm) Dimension ...
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Si 550 6. Top Marking 6.1. Si550 Top Marking 6.2. Top Marking Explanation Line Position 1 1–10 “SiLabs”+ Part Family Number, 550 (First 3 characters in part number) 2 1–10 Si550: Option1+Option2+Freq(6007)+Temp 3 Trace Code Pin 1 orientation mark (dot) ...
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OCUMENT HANGE IST Revision 0.6 to Revision 1.0 Updated Table 4 on page 3. Updated 2.5 V/3.3 V and 1.8 V CML output level specifications. Updated Table 5 on page 4. Removed the words ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...