KSZ8041FTL-S Micrel, KSZ8041FTL-S Datasheet
KSZ8041FTL-S
Specifications of KSZ8041FTL-S
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KSZ8041FTL-S Summary of contents
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... The KSZ8041TL represents a new level of features and performance and is an ideal choice of physical layer transceiver for 10Base-T/100Base-TX applications. The KSZ8041FTL has all the identical rich features of the KSZ8041TL plus 100Base-FX support for fiber and media converter applications. Both KSZ8041TL and KSZ8041FTL are available in 48- pin, lead-free TQFP packages (See Ordering Information) ...
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... Robust operation over standard cables • LinkMD ® TDR-based cable diagnostics for identification of faulty copper cabling • Fiber support: 100Base-FX (KSZ8041FTL only), Back- to-Back mode (KSZ8041FTL and KSZ8041TL) • MII interface support • RMII interface support with external 50MHz system clock • ...
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... Micrel, Inc. Revision History Revision Date Summary of Changes 1.0 12/21/06 Data sheet created. 1.1 4/27/07 Added maximum MDC clock speed. Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pull- downs. Changed Model Number in Register 3h – PHY Identifier 2. Changed polarity (swapped definition) of DUPLEX strapping pin. ...
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... Micrel, Inc. Contents Pin Configuration .................................................................................................................................................................. 8 Pin Description .................................................................................................................................................................... 10 Strapping Options............................................................................................................................................................... 15 Functional Description ....................................................................................................................................................... 17 100Base-TX Transmit....................................................................................................................................................... 17 100Base-TX Receive........................................................................................................................................................ 17 PLL Clock Synthesizer...................................................................................................................................................... 17 Scrambler/De-scrambler (100Base-TX only).................................................................................................................... 17 10Base-T Transmit ........................................................................................................................................................... 17 10Base-T Receive ............................................................................................................................................................ 18 SQE and Jabber Function (10Base-T only)...................................................................................................................... 18 Auto-Negotiation ............................................................................................................................................................... 18 MII Management (MIIM) Interface .................................................................................................................................... 20 Interrupt (INTRP) .............................................................................................................................................................. 20 MII Data Interface ............................................................................................................................................................. 20 MII Signal Definition ...
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... Power Management.......................................................................................................................................................... 29 Power Saving Mode.................................................................................................................................................... 29 Power Down Mode...................................................................................................................................................... 29 Reference Clock Connection Options .............................................................................................................................. 30 Reference Circuit for Power and Ground Connections .................................................................................................... 31 100Base-FX Fiber Operation (KSZ8041FTL only) ........................................................................................................... 32 Fiber Signal Detect ..................................................................................................................................................... 32 Far-End Fault............................................................................................................................................................... 32 Back-to-Back Media Converter......................................................................................................................................... 33 MII Back-to-Back Mode .............................................................................................................................................. 33 RMII Back-to-Back Mode............................................................................................................................................ 34 Register Map ...
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... Figure 7. 50MHz Oscillator Reference Clock for RMII Mode............................................................................................... 30 Figure 8. 125MHz Oscillator Reference Clock for SMII Mode ............................................................................................. 30 Figure 9. KSZ8041TL/FTL Power and Ground Connections............................................................................................... 31 Figure 10. KSZ8041FTL / KSZ8041TL Back-to-Back Media Converter .............................................................................. 33 Figure 11. MII SQE Timing (10Base-T) ............................................................................................................................... 45 Figure 12. MII Transmit Timing (10Base-T) ......................................................................................................................... 46 Figure 13. MII Receive Timing (10Base-T) .......................................................................................................................... 47 Figure 14 ...
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... Micrel, Inc. List of Tables Table 1. MII Management Frame Format ............................................................................................................................ 20 Table 2. MII Signal Definition ............................................................................................................................................... 21 Table 3. RMII Signal Description.......................................................................................................................................... 23 Table 4. SMII Signal Description.......................................................................................................................................... 24 Table 5. SMII TX Bit Description .......................................................................................................................................... 25 Table 6. SMII TXD[0:7] Encoding Table .............................................................................................................................. 25 Table 7. SMII RX Bit Description.......................................................................................................................................... 26 Table 8. SMII RXD[0:7] Encoding Table .............................................................................................................................. 26 Table 9. MDI/MDI-X Pin Definition ....................................................................................................................................... 27 Table 10 ...
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... Micrel, Inc. Pin Configuration GND 2 GND 3 GND 4 VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX April 2007 KSZ8041TL 48-Pin TQFP 8 KSZ8041TL/FTL TXD1 / TXD[1] / SYNC TXD0 / TXD[ TXEN / TX_EN TXC INTRP VDD_1 ...
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... VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX April 2007 KSZ8041FTL 48-Pin TQFP 9 KSZ8041TL/FTL TXD1 / TXD[1] / SYNC TXD0 / TXD[ TXEN / TX_EN TXC INTRP VDD_1.8 GND RXER / RX_ER / ISO RXC RXDV / CRSDV / CONFIG2 VDDIO_3 ...
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... Micrel, Inc. Pin Description Pin Number Pin Name Type 1 GND 2 GND 3 GND 4 VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX- 12 TX+ 13 GND REFCLK / CLOCK 16 REXT 17 GND 18 MDIO 19 MDC 20 RXD3 / PHYAD0 21 RXD2 / PHYAD1 22 RXD1 / RXD[1] / PHYAD2 April 2007 (1) Pin Function ...
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... Micrel, Inc. Pin Number Pin Name Type 23 RXD0 / RXD[ DUPLEX 24 GND 25 VDDIO_3.3 26 VDDIO_3.3 27 RXDV / CRSDV / CONFIG2 28 RXC 29 RXER / RX_ER / ISO 30 GND 31 VDD_1.8 32 INTRP 33 TXC 34 TXEN / TX_EN 35 TXD0 / TXD[ TXD1 / TXD[1] / SYNC 37 GND 38 TXD2 39 TXD3 40 COL / CONFIG0 41 CRS / CONFIG1 April 2007 ...
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... Micrel, Inc. Pin Number Pin Name Type 42 LED0 / (KSZ8041TL) NWAYEN 42 LED0 / (KSZ8041FTL) NWAYEN April 2007 (1) Pin Function Ipu/O LED Output: Programmable LED0 Output / Config Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up / reset. See “Strapping Options” section for details. The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows ...
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... Micrel, Inc. Pin Number Pin Name Type 43 LED1 / (KSZ8041TL) SPEED 43 LED1 / (KSZ8041FTL) SPEED / no FEF April 2007 (1) Pin Function Ipu/O LED Output: Programmable LED1 Output / Config Mode: Latched as SPEED (register 0h, bit 13) during power-up / reset. See “Strapping Options” section for details. ...
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... Micrel, Inc. Pin Number Pin Name 47 RST (KSZ8041TL) 48 FXSD / (KSZ8041FTL) FXEN Notes Power supply. Gnd = Ground Input Output. I/O = Bi-directional. Ipd = Input with internal pull-down (40K +/-30%). Ipu = Input with internal pull-up (40K +/-30%). Opu = Output with internal pull-up (40K +/-30%). Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. ...
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... CONFIG1 40 CONFIG0 29 ISO 43 SPEED (KSZ8041TL) 43 SPEED / (KSZ8041FTL) no FEF April 2007 (1) Pin Function Ipd/O The PHY Address is latched at power-up / reset and is configurable to any value from Ipd/O The default PHY Address is 00001. Ipu/O PHY Address bits [4:3] are always set to ‘00’. ...
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... NWAYEN (KSZ8041TL) 42 NWAYEN (KSZ8041FTL) Note: 1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise. Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high ...
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... Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. The KSZ8041FTL has all the identical rich features of the KSZ8041TL plus 100Base-FX fiber support. 100Base-TX Transmit The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission ...
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... Micrel, Inc. 10Base-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and RX- inputs from falsely trigger the decoder ...
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... Micrel, Inc. Start Auto Negotiation Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode April 2007 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set Figure 1. Auto-Negotiation Flow Chart 19 KSZ8041TL/FTL ...
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... Micrel, Inc. MII Management (MIIM) Interface The KSZ8041TL/FTL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8041TL/FTL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings ...
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... Micrel, Inc. MII Signal Definition The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information. Direction MII (with respect to PHY, Signal Name KSZ8041TL/FTL signal) TXC Output TXEN Input TXD[3:0] Input RXC Output RXDV Output ...
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... Micrel, Inc. Receive Data Valid (RXDV) RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0]. • In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains asserted until the end of the frame. ...
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... Micrel, Inc. RMII Signal Definition The following table describes the RMII signals. Refer to RMII Specification for detailed information. Direction RMII (with respect to PHY, Signal Name KSZ8041TL/FTL signal) REF_CLK Input TX_EN Input TXD[1:0] Input CRS_DV Output RXD[1:0] Output RX_ER Output Reference Clock (REF_CLK) REF_CLK is sourced by the MAC or system board ...
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... Micrel, Inc. Collision Detection The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV. Serial MII (SMII) Data Interface The Serial Media Independent Interface (SMII) is the lowest pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: • ...
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... Micrel, Inc. The following figure and table shows the transmit data/control format for each segment: CLOCK SYNC TX TX_ER TX_EN SMII TX Bit TX_ER TX_EN TXD[0:7] TX_ER TX_EN TXD0 X 0 Use to force an error in a direct MAC-to- MAC connection X 1 One Data Byte Receive Data and Control (RX) RX provides receive data and control information from PHY-to-MAC in 10-bit segments. • ...
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... Micrel, Inc. The following figure and table shows the receive data/control format for each segment: CLOCK SYNC RX CRS RX_DV SMII RX Bit CRS RX_DV RXD[0:7] CRS RX_DV RXD0 X 0 RX_ER from pervious frame X 1 One Data Byte Collision Detection Collisions occur when CRS and TX_EN are simultaneously asserted. The MAC regenerates the MII collision signal from CRS and TX_EN ...
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... Micrel, Inc. HP Auto MDI/MDI-X HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041TL/FTL and its link partner. This feature allows the KSZ8041TL/FTL to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041TL/FTL accordingly ...
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... Micrel, Inc. Crossover Cable A crossover cable connects a MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices). April 2007 10/100 Ethernet Media Dependent Interface 1 Crossover ...
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... Micrel, Inc. ® LinkMD Cable Diagnostics ® The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems, such as open circuits, short circuits and impedance mismatches. ® LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs, and then analyzing the shape of the reflected signal ...
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... Micrel, Inc. Reference Clock Connection Options A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041TL/FTL. The reference clock is 25 MHz for MII mode, 50 MHz for RMII mode, and 125 MHz for SMII mode. The following three figures illustrate how to connect the reference clock REFCLK / CLOCK (pin 9) and XO (pin 8) of the KSZ8041TL/FTL ...
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... Micrel, Inc. Reference Circuit for Power and Ground Connections The KSZ8041TL/FTL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground connections are shown in the following figure and table. Figure 9. KSZ8041TL/FTL Power and Ground Connections Power Pin Pin Number V1 ...
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... A Far-End Fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KSZ8041FTL detects a FEF when its FXSD input (pin 48) is between 1V and 1.8V. When a FEF is detected, the KSZ8041FTL signals its fiber link partner that a FEF has occurred by transmitting a repetitive pattern of 84-ones and 1- zero. This pattern is used to inform the fiber link partner that there is a faulty link on its transmit side. By default, FEF is enabled. FEF is disabled by strapping “ ...
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... The KSZ8041FTL and KSZ8041TL support MII Back-to-Back mode and RMII Back-to-Back mode for media conversion. MII Back-to-Back Mode The KSZ8041FTL and KSZ8041TL are configured in MII Back-to-Back mode after it is power-up or reset with the following: • CONFIG[2:0] (pins 27, 41, 40) set to ‘110’ for both KSZ8041FTL and KSZ8041TL. ...
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... Micrel, Inc. RMII Back-to-Back Mode The KSZ8041FTL and KSZ8041TL are configured in RMII Back-to-Back mode after it is power-up or reset with the following: • CONFIG[2:0] (pins 27, 41, 40) set to ‘101’ for both KSZ8041FTL and KSZ8041TL. • A common 50 MHz reference clock connected to REFCLK (pin 15) of both KSZ8041FTL and KSZ8041TL. ...
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... Micrel, Inc. Register Map Register Number (Hex) Description 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Link Partner Next Page Ability 9h – 14h Reserved 15h RXER Counter 16h – 1Ah ...
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... Micrel, Inc. Address Name Description 0.8 Duplex Mode 1 = Full-duplex 0 = Half-duplex 0.7 Collision Test 1 = Enable COL test 0 = Disable COL test 0.6:1 Reserved 0.0 Disable 0 = Enable transmitter Transmitter 1 = Disable transmitter Register 1h – Basic Status 1.15 100Base- capable 0 = Not T4 capable 100Base-TX 1. Capable of 100Mbps full-duplex Full Duplex 0 = Not capable of 100Mbps full-duplex 1 ...
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... Micrel, Inc. Address Name Description Register 3h – PHY Identifier 2 3.15:10 PHY ID Assigned to the 19th through 24 Number Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) 3.9:4 Model Number Six bit manufacturer’s model number Revision 3.3:0 Four bit manufacturer’s model number Number Register 4h – ...
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... Micrel, Inc. Address Name Description 5.9 100Base- capable capability 5.8 100Base- 100Mbps full-duplex capable Full-Duplex 100Mbps full-duplex capability 5.7 100Base- 100Mbps half-duplex capable Half-Duplex 100Mbps half-duplex capability 5.6 10Base 10Mbps full-duplex capable Full-Duplex 10Mbps full-duplex capability 5.5 10Base 10Mbps half-duplex capable ...
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... Micrel, Inc. Address Name Description 8.14 Acknowledge 1 = Successful receipt of link word successful receipt of link word 8.13 Message Page 1 = Message page 0 = Unformatted page 8.12 Acknowledge2 1 = Able to act on the information 0 = Not able to act on the information 8.11 Toggle 1 = Previous value of transmitted link code 0 = Previous value of transmitted link code 8 ...
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... LED1 : Activity [10] = Reserved [11] = Reserved 1e.13 Polarity 0 = Polarity is not reversed 1 = Polarity is reversed 1e.12 Far-End Fault 0 = Far-End Fault not detected Detect 1 = Far-End Fault detected This bit applies to KSZ8041FTL fiber only. 1e.11 MDI/MDI MDI State 1 = MDI-X 1e.10:8 Reserved 1e.7 Remote 0 = Normal mode loopback 1 = Remote (analog) loop back is enable 1e ...
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... Micrel, Inc. Address Name Description Register 1Fh – PHY Control 2 1f.15 HP_MDIX 0 = Micrel Auto MDI/MDI-X mode Auto MDI/MDI-X mode 1f.14 MDI/MDI-X When Auto MDI/MDI-X is disabled, Select 0 = MDI Mode 1 = MDI-X Mode Pairswap 1f. Disable auto MDI/MDI-X Disable 0 = Enable auto MDI/MDI-X 1f.12 Energy Detect 1 = Presence of signal on RX+/- analog wire signal detected on RX+/- 1f ...
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... Micrel, Inc. Address Name Description 1f.0 Disable Data 1 = Disable scrambler Scrambling 0 = Enable scrambler Note Read/Write Read only Self-cleared Latch high Latch low. April 2007 (1) Default Mode KSZ8041TL/FTL M9999-042707-1.1 ...
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... Micrel, Inc. Absolute Maximum Ratings Supply Voltage ( ........................ -0.5V to +2.4V DD_1.8, DDA_1.8, 1.8_OUT ( ................................... -0.5V to +4.0V DDIO_3.3, DDA_3.3 Input Voltage (all inputs) ............................... -0.5V to +4.0V Output Voltage (all outputs) .......................... -0.5V to +4.0V Lead Temperature (soldering, 10sec.)....................... 260°C Storage Temperature (T ) ..........................-55°C to +150°C s Electrical Characteristics Symbol Parameter (4) Supply Current ...
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... Micrel, Inc. Notes: 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. ...
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... Micrel, Inc. Timing Diagrams MII SQE Timing (10Base-T) TXC TXEN COL Timing Parameter SQE t SQEP April 2007 SQE t SQEP Figure 11. MII SQE Timing (10Base-T) Description TXC period TXC pulse width low TXC pulse width high ...
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... Micrel, Inc. MII Transmit Timing (10Base-T) TXC TXEN t SU2 TXD[3:0] CRS Timing Parameter SU1 t SU2 t HD1 t HD2 t CRS1 t CRS2 April 2007 HD2 t t SU1 HD1 t CRS1 Figure 12. MII Transmit Timing (10Base-T) Description TXC period TXC pulse width low ...
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... Micrel, Inc. MII Receive Timing (10Base-T) Timing Parameter RLAT April 2007 Figure 13. MII Receive Timing (10Base-T) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) output delay from rising edge of RXC CRS to (RXD[3:0], RXER, RXDV) latency Table 16 ...
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... Micrel, Inc. MII Transmit Timing (100Base-TX) Timing Parameter SU1 t SU2 t HD1 t HD2 t CRS1 t CRS2 April 2007 Figure 14. MII Transmit Timing (100Base-TX) Description TXC period TXC pulse width low TXC pulse width high TXD[3:0] setup to rising edge of TXC TXEN setup to rising edge of TXC ...
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... Micrel, Inc. MII Receive Timing (100Base-TX) Timing Parameter RLAT April 2007 Figure 15. MII Receive Timing (100Base-TX) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) output delay from rising edge of RXC CRS to (RXD[3:0], RXER, RXDV) latency Table 18 ...
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... Micrel, Inc. RMII Timing Receive Tim ing REFCLK CRSDV RXD[1:0] Timing Parameter t cyc April 2007 tcyc t1 t2 Figure 16. RMII Timing – Data Received from RMII ...
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... Micrel, Inc. Auto-Negotiation Timing tiatio n F ast Timing Parameter t BTB t FLPW CTD t CTC Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters April 2007 rst ...
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... Micrel, Inc. MDC/MDIO Timing MDC MDIO (PHY input) MDIO (PHY output) Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising edge of MDC ...
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... Micrel, Inc. Reset Timing The KSZ8041TL/FTL reset timing requirement is summarized in the following figure and table. Supply Voltage RST# Strap-In Value Strap-In / Output Pin Parameter After the de-assertion of reset recommended to wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) Interface ...
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... Micrel, Inc. Reset Circuit The following reset circuit is recommended for powering up the KSZ8041TL/FTL if reset is triggered by the power supply. KSZ8041TL/FTL The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA). At power-on-reset and D1 provide the necessary ramp rise time to reset the KSZ8041TL/FTL device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up ...
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... Micrel, Inc. The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins. April 2007 Pull-up KSZ8041TL/FTL LED pin Float KSZ8041TL/FTL LED pin Pull-down KSZ8041TL/FTL LED pin Figure 23. Reference Circuits for LED Strapping Pins ...
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... Micrel, Inc. Selection of Isolation Transformer A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit inductance (min.) Leakage inductance (max.) Inter-winding capacitance (max.) D ...
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... Micrel, Inc. Package Information Note: ALL DIMENSIONS ARE IN MILLIMETERS. April 2007 ...
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... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to April 2007 fully indemnify Micrel for any damages resulting from such use or sale ...