W5100 WIZnet, W5100 Datasheet - Page 38

• Manufacturer Part Number: W5100
• Description: Ethernet ICs 3-IN-1 ENET CONTR TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W5100

• Rohs: yes
• Product: Ethernet Controllers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 80 C
• Package / Case: LQFP-80
• Ethernet Connection Type: 10Base-T, 100Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Standard Supported: 802.3, 802.3u

© Copyright 2009-2010 WIZnet Co., Inc. All rights reserved.
5. Functional Descriptions
By setting some register and memory operation, W5100 provides internet connectivity. This
chapter describes how it can be operated.
5.1 Initialization
For the W5100 operation, select and utilize appropriate registers shown below.
For more information of above registers, refer to the “Register Descriptions”.
Below register is for basic network configuration information to be configured according to
the network environment.
The Source Hardware Address Register (SHAR) is the H/W address to be used in MAC layer, and
can be used with the address that manufacturer has been assigned. The MAC address can be
assigned from IEEE. For more detail, refer to IEEE homepage.
This stage sets the socket tx/rx memory information. The base address and mask address of
each socket are fixed and saved in this stage.
In case of, assign 2K rx memory per socket.
{
memory.
RMSR = 0x55;
gS0_RX_BASE = chip_base_address + RX_memory_base_address(0x6000);
gS0_RX_MASK = 2K – 1 ;
gS1_RX_BASE = gS0_BASE + (gS0_MASK + 1);
gS1_RX_MASK = 2K – 1 ;

1. Mode Register (MR)
2. Interrupt Mask Register (IMR)
3. Retry Time-value Register (RTR)
4. Retry Count Register (RCR)

1. Gateway Address Register (GAR)
2. Source Hardware Address Register (SHAR)
3. Subnet Mask Register (SUBR)
4. Source IP Address Register (SIPR)

Basic Setting
Setting network information
Set socket memory information
// assign 2K rx memory per socket.
// 0x07FF, for getting offset address within assigned socket 0 RX
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