W3150A+

Manufacturer Part NumberW3150A+
DescriptionEthernet ICs ENET CONTR TCP/IP+MAC
ManufacturerWIZnet
W3150A+ datasheet
 


Specifications of W3150A+

RohsyesProductEthernet Transceivers
Supply Voltage - Max3.6 VSupply Voltage - Min3 V
Maximum Operating Temperature+ 80 CPackage / CaseLQFP-64
Ethernet Connection Type10Base-T, 100Base-TXMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMT  
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W3150A+ Datasheet
Ver. 2.0.4
© 2006 WIZnet Co., Inc. All Rights Reserved.
For more information, visit our website at
http://www.wiznet.co.kr

W3150A+ Summary of contents

  • Page 1

    ... W3150A+ Datasheet © 2006 WIZnet Co., Inc. All Rights Reserved. For more information, visit our website at Ver. 2.0.4 http://www.wiznet.co.kr ...

  • Page 2

    ... Modify explanation of RECV_INT in Sn_IR register (P. 27) Replace reset value of Sn_DHAR register (0x00 to 0xFF, P. 30) Modify explanation of Sn_DIPR, Sn_DPORT register(P. 30) Replace reset value of Sn_MSS register (0xFFFF to 0x0000, P. 31) Modify figure of W3150A+ AC Characteristics(P. 58,59,60,62,63) Modify figure of W3150A+ AC Characteristics (Added item NO.7 SCLK high to /SS high ...

  • Page 3

    ... WIZnet’s Online Technical Support If you have something to ask about WIZnet Products, Write down your question on Q&A Board of ‘Support’ menu in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an answer as soon as possible. © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 4

    ... W3150A+ Datasheet Description The W3150A LSI of hardware protocol stack that provides an easy, low-cost solution for high-speed Internet connectivity for digital devices by allowing simple installation of TCP/IP stack in the hardware. The W3150A+ offers a quick and easy way to add Ethernet networking functionality to any products. ...

  • Page 5

    ... Block Diagram © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 6

    ... Block Diagram................................................................................................................ 4 Table of Contents............................................................................................................ 5 Pin Assignment ......................................................................................................... 7 1. MII Signal Description ..................................................................................... 8 1.1. MCU Interface Signal Description........................................................................ 9 1.2. Miscellaneous Signal Description ...................................................................... 11 1.3. Power Supply Signal Description....................................................................... 12 1.4. Memory map.......................................................................................................... 13 2. W3150A+ Registers .................................................................................................. 14 3. Common Registers ....................................................................................... 14 3.1. Socket Registers.......................................................................................... 15 3.2. Register Descriptions................................................................................................ 19 4. Common Registers ....................................................................................... 19 4.1. Socket Registers.......................................................................................... 25 4.2. Functional Description.............................................................................................. 35 5. ...

  • Page 7

    ... Register/Memory WRITE Timing ..................................................................60 7.4.4. SPI Timing ............................................................................................61 7.4.5. MII(Media Independent Interface) Timing .......................................................62 IR Reflow Temperature Profile (Lead-Free) ..................................................................... 64 8. Package Description................................................................................................. 65 9. © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 8

    ... A[13] or /SS 6 A[12] or MOSI 7 A[11] or MISO 8 A[10] 9 A[9] 10 A[8] 11 TEST 12 GND 13 A[7] 14 A[ © Copyright 2006 WIZnet Co., Inc. All rights reserved W3150A+ 64 LQFP ...

  • Page 9

    ... RXD[3:0]. If signal is detected low at the end of the valid packet, the signal is valid on the rising of the RXC. 43 RXD[3] Receive Data 42 RXD[2] These pins receive Nibble NRZ data from the PHY device synchronously with I 41 RXD[1] RXC when RXDV is asserted. 40 RXD[0] © Copyright 2006 WIZnet Co., Inc. All rights reserved. Description - 8 - ...

  • Page 10

    ... Asserting this pin low for at least 2us will force a reset process to occur which will result in all internal registers re-initializing to their default states. CLOCK This pin is the Primary clock required for internal operation of W3150A+. 25MHz is required. In general, PHY driving clock can be shared for saving cost. 35 ...

  • Page 11

    ... This signal is active low. WRITE ENABLE Strobe from MCU to write an internal register/memory selected by A[14:0]. 62 /WR I Data is latched into the W3150A+ on the rising edge of this input. This signal is active low. READ ENABLE 63 /RD I Strobe from MCU to read an internal register/memory selected by A[14:0]. ...

  • Page 12

    ... This pin is internally pulled down for previous W3150A users. Even if there 33 SPI_EN signal connection to this pin, it asserts low internally. Thereby, in case of change to W3150A+, there is no effort to change previous board design. Low = SPI Mode Disable High = SPI Mode Enable FACTORY TEST INPUT 4,12,56, ...

  • Page 13

    ... AVIN 57 VOUT 3, 13, 23, 36, 45, 54 GND VOUT Figure 1-1. Reference Schematic for Power input © Copyright 2006 WIZnet Co., Inc. All rights reserved. I/O POSITIVE 3.3V SUPPLY PINS 1.8V power input 1.8V power supply 1.8V Analog power input 1.8V power supply for analog circuit ; should be well decoupled. Refer Figure 1-1. Reference Schematic for Power input. ...

  • Page 14

    ... Memory map W3150A+ is composed of Common Register, Socket Register, TX Memory, and RX Memory. Each fields are shown as below. 0x0000 0x0030 0x0400 0x0800 0x4000 0x6000 0x8000 © Copyright 2006 WIZnet Co., Inc. All rights reserved. Common Registers Reserved Socket Registers Reserved TX memory RX memory - 13 - ...

  • Page 15

    ... W3150A+ Registers 3.1. Common Registers Address Register 0x0000 Mode (MR) Gateway Address 0x0001 (GAR0) 0x0002 (GAR1) 0x0003 (GAR2) 0x0004 (GAR3) Subnet mask Address 0x0005 (SUBR0) 0x0006 (SUBR1) 0x0007 (SUBR2) 0x0008 (SUBR3) Source Hardware Address 0x0009 (SHAR0) 0x000A (SHAR1) 0x000B (SHAR2) 0x000C (SHAR3) 0x000D ...

  • Page 16

    ... Socket 0 Maximum Segment Size 0x0412 (S0_MSSR0) 0x0413 (S0_MSSR1) Socket 0 Protocol in IP Raw mode 0x0414 (S0_PROTO) © Copyright 2006 WIZnet Co., Inc. All rights reserved. Address Register 0x0415 Socket 0 IP TOS (S0_TOS) 0x0416 Socket 0 IP TTL (S0_TTL) 0x0417 ~ Reserved 0x041F ...

  • Page 17

    ... Socket 1 Maximum Segment Size 0x0512 (S1_MSSR0) 0x0513 (S1_MSSR1) Socket 1 Protocol in IP Raw mode 0x0514 (S1_PROTO) © Copyright 2006 WIZnet Co., Inc. All rights reserved. Address Register 0x0515 Socket 1 IP TOS (S1_TOS) 0x0516 Socket 1 IP TTL (S1_TTL) 0x0517 ~ Reserved 0x051F ...

  • Page 18

    ... Socket 2 Maximum Segment Size 0x0612 (S2_MSSR0) 0x0613 (S2_MSSR1) Socket 2 Protocol in IP Raw mode 0x0614 (S2_PROTO) © Copyright 2006 WIZnet Co., Inc. All rights reserved. Address Register 0x0615 Socket 2 IP TOS (S2_TOS) 0x0616 Socket 2 IP TTL (S2_TTL) 0x0617 ~ Reserved 0x061F ...

  • Page 19

    ... Socket 3 Maximum Segment Size 0x0712 (S3_MSSR0) 0x0713 (S3_MSSR1) Socket 3 Protocol in IP Raw mode 0x0714 (S3_PROTO) © Copyright 2006 WIZnet Co., Inc. All rights reserved. Address Register 0x0715 Socket 3 IP TOS (S3_TOS) 0x0716 Socket 3 IP TTL (S3_TTL) 0x0717 ~ Reserved 0x071F ...

  • Page 20

    ... At the Indirect Bus I/F mode, if this bit is set as ‘1’, the address will be automatically increased by 1 whenever Read and Write are performed. For more detail, refer to 6.1.2 Indirect Bus IF Mode. Indirect Bus I/F mode 0 IND 0 : Disable Indirect bus I/F mode [Read/Write] [Address] [Reset value] * © Copyright 2006 WIZnet Co., Inc. All rights reserved PPPoE Description - 19 - ...

  • Page 21

    ... SIPR (Source IP Address Register) [R/W] [0x000F – 0x0012] [0x00] This register sets up the Source IP address. Ex) in case of “192.168.0.3” 0x000F 192 (0xC0) © Copyright 2006 WIZnet Co., Inc. All rights reserved. 0x0002 0x0003 168 (0xA8) 0 (0x00) 0x0006 0x0007 255 (0xFF) ...

  • Page 22

    ... CONFLICT It is set as ‘1’, when there is ARP request with same IP address as Source IP address. This bit is cleared to ‘0’ by Destination unreachable W3150A+ will receive ICMP(Destination Unreachable) packet if not-existing destination IP address is transmitted during UDP data transmission. (Refer to 5.2.2. UDP). In this 6 UNREACH case, the IP address and the port number will be saved in Unreachable IP Address (UIPR) and Unreachable Port Register (UPORT), and the bit will be set as ‘ ...

  • Page 23

    ... Ex) For 400ms configuration, set as 4000(0x0FA0) 0x0017 0x0F Re-transmission will occur if there is no response from the remote peer to the commands of CONNECT, DISCON, CLOSE, SEND, SEND_MAC and SEND_KEEP, or the response is delayed. © Copyright 2006 WIZnet Co., Inc. All rights reserved Reserved IM_IR3 ...

  • Page 24

    ... TMSR(TX Memory Size Register) [R/W] [0x001B] [0x55] This register is used in assigning total 8K TX Memory to sockets. Configuration can be done in the same way of RX Memory Size Register (RMSR). The initial value is 0x55 and assign 2K memory to 4 sockets respectively. © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 25

    ... PATR (Authentication Type in PPPoE mode) [R] [0x001C-0x001D] [0x0000] This register notifies authentication method that has been agreed at the connection with PPPoE Server. W3150A+ supports two types of Authentication method - PAP and CHAP. Value 0xC023 0xC223 PTIMER (PPP Link Control Protocol Request Timer Register) [R/W] [0x0028] [0x28] This register indicates the duration for sending LCP Echo Request ...

  • Page 26

    ... IGMP version using IGMP version applied only in case of MULTI 4 Reserved Reserved n is socket number ( 3). 1 [Read/Write] [address of socket 0, address of socket 1, address of socket 2, address of socket 3] [Reset value] 2 © Copyright 2006 WIZnet Co., Inc. All rights reserved Description bit is ‘1’ ...

  • Page 27

    ... Timeout interrupt will occur. For more detail, refer to 5.2.1.1. SERVER. 0x08 DISCON * In case of using CLOSE command instead of DISCON, only the value of Socket n Status Register(Sn_SR) is changed to SOCK_CLOSED without the connection termination process. © Copyright 2006 WIZnet Co., Inc. All rights reserved Meaning 0 0 Closed ...

  • Page 28

    ... It is set as ‘1’ if send operation is completed. TIMEOUT It is set as ‘1’ if Timeout occurs during connection establishment or termination 3 and data transmission. 2 RECV It is set as ‘1’ whenever w3150a+ receives data. * Difference from W3150A ** SEND_OK Interrupt is added in W3150A+ © Copyright 2006 WIZnet Co., Inc. All rights reserved. Pointer Register(Sn_TX_WR), 5 ...

  • Page 29

    ... CON It is set as ‘1’ if connection is established. Sn_SR (Socket n Status Register) [R] [0x0403, 0x0503, 0x0603, 0x0703] [0x00] This register has the status vaule of socket n. The main status is shown in the below diagram. © Copyright 2006 WIZnet Co., Inc. All rights reserved. Figure 4-1. State Diagram - 28 - ...

  • Page 30

    ... SOCK_LAST_ACK 0x11 SOCK_ARP 0x21 0x31 © Copyright 2006 WIZnet Co., Inc. All rights reserved. Description It is shown in case that CLOSE commands are given to Sn_CR, and Timeout interrupt is asserted or connection is terminated shown in case that Sn_MR is set as TCP and OPEN commands are given to Sn_CR. ...

  • Page 31

    ... Connect command. In passive mode, W3150A+ sets up the connection and then is internally updated with peer port number. In UDP mode, this register value decided to user’s written value after receiving peer’s ARP response. ...

  • Page 32

    ... Ex) In case of 2048(0x0800) in S0_TX_FSR, 0x0420 0x08 Total size can be decided according to the value of TX Memory Size Register. In the process of transmission, it will be reduced by the size of transmitting data, and automatically increased after transmission finished. © Copyright 2006 WIZnet Co., Inc. All rights reserved. 0x0413 0xB4 that IP ...

  • Page 33

    ... After that, be sure to increase the Sn_TX_WR value as much as the data size, that indicates the size of writing data. Finally, give SEND command to Sn_CR(Socket n Command Register). Refer to the psedo code of the transmission part on 5.2.1.1. TCP Server mode if the detail is needed. © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 34

    ... Figure 4-2. Calculate physical address - 33 - © Copyright 2006 WIZnet Co., Inc. All rights reserved. ...

  • Page 35

    ... Must not increase more than the size of received data. So must check Sn_RX_RSR before receiving process.) Finally, give RECV command to Sn_CR(Socket n Command Register). Refer to the psedo code of the receiving part on 5.2.1.1. TCP Server mode if the detail is needed. © Copyright 2006 WIZnet Co., Inc. All rights reserved. 0x0427 0x00 ...

  • Page 36

    ... Functional Description By setting some register and memory operation, W3150A+ provides internet connectivity. This chapter describes how it can be operated. 5.1. Initialization Setting network information Below register is for basic network configuration information to be configured according to the network environment. 1. Gateway Address Register (GAR) 2. Source Hardware Address Register (SHAR) 3 ...

  • Page 37

    ... TMSR = 0x06; // assign 4K,2K,1K,1K rx memory per socket. Same method, set gS0_TX_BASE, gS2_TX_MASK, gS3_TX_BASE and gS3_TX_MASK. } © Copyright 2006 WIZnet Co., Inc. All rights reserved. gS0_TX_MASK, gS1_TX_BASE, Figure 5-1. In case of RMSR = 0x55 Figure 5-2. In case of TMSR = 0x55 - 36 - gS1_TX_MASK, gS2_TX_BASE, ...

  • Page 38

    ... Data communication Data communication is available through TCP ,UDP ,IP-Raw and MAC-Raw . In order to select it, configure protocol field of Socket n Mode Register(Sn_MR) of the commnucation sockets (W3150A+ supports total 4 sockets). 5.2.1. TCP TCP is connection oriented communication method that will establish connection in advance and deliver the data through the connection by using IP Address and Port number of the systems. There are two methods to establish the connection ...

  • Page 39

    ... Sn_CR = LISTEN; if (Sn_SR != SOCK_LISTEN) Sn_CR = CLOSE; goto START; } ESTABLISHED ? If received connection request from remote peer (the stauts of SOCK_SYNRECV), W3150A+ sends ACK packet and changes to SOCK_ESTABLISHED status. This status can be checked as below. First method : { If (Sn_IR(CON bit) == ‘1’) goto ESTABLISHED stage; ...

  • Page 40

    ... RX memory */ if ( (get_offset + get_size) > (gSn_RX_MASK + copy upper_size bytes of get_start_address to destination_addr */ upper_size = (gSn_RX_MASK + 1) – get_offset; memcpy(get_start_address, destination_addr, upper_size); /* update destination_addr*/ destination_addr += upper_size; /* copy left_size bytes of gSn_RX_BASE to destination_addr */ left_size = get_size – upper_size; memcpy(gSn_RX_BASE, destination_addr, left_size); } else © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 41

    ... TX memory */ if ( (get_offset + send_size) > (gSn_TX_MASK + copy upper_size bytes of source_addr to get_start_address */ upper_size = (gSn_TX_MASK + 1) – get_offset; memcpy(source_addr, get_start_address, upper_size); /* update source_addr*/ source_addr += upper_size; /* copy left_size bytes of source_addr to gSn_TX_BASE */ left_size = send_size – upper_size; memcpy(source_addr, gSn_TX_BASE, left_size); } else { © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 42

    ... DISCON command */ Sn_CR = DISCON; } ESTABLISHED : CLOSED ? No connection state at all. It can be checked as below, First method : { If (Sn_IR(DISCON bit) == ‘1’) goto CLOSED stage this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 43

    ... If (Sn_SR == SOCK_CLOSED) goto CLOSED stage; } Socket Close This process should be processed in case that connection is closed after data exchage, socket should be closed with Timeout occurrence, or forcible disconnection is necessary due to abonormal operation set CLOSE command */ Sn_CR = CLOSE; } © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 44

    ... Refer to 5.2.1.1 SERVER (The operation is same as SERVER). CONNECT Send connection request to remote HOST(SERVER below Write the value of server_ip, server_port to the Socket n Destination IP Address Register(Sn_DIPR), Socket n Destination Port Register(Sn_DPORT). */ Sn_DIPR = server_ip; Sn_DPORT = server_port; /* set CONNECT command */ Sn_CR = CONNECT; } © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 45

    ... In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR Second method : { If (Sn_SR == SOCK_CLOSED) goto CLOSED stage; } ESTABLISHED Refer to 5.2.1.1. SERVER (The operation is same as SERVER mode) © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 46

    ... The value of Source Port can be appropriately delivered when remote HOST knows it. */ Sn_PORT = source_port; /* sets OPEN command */ Sn_CR = OPEN; /* Check if the value of Socket n Status Register(Sn_SR) is SOCK_UDP (Sn_SR != SOCK_UDP) Sn_CR = CLOSE; goto START; } © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 47

    ... Copyright 2006 WIZnet Co., Inc. All rights reserved. Destination Port (2) Data size (2) (*data size except for 8byte of header ...

  • Page 48

    ... Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 49

    ... TX memory */ if ( (get_offset + send_size) > (gSn_TX_MASK + copy upper_size bytes of source_addr to get_start_address */ upper_size = (gSn_TX_MASK + 1) – get_offset; memcpy(source_addr, get_start_address, upper_size); /* update source_addr*/ source_addr += upper_size; /* copy left_size bytes of source_addr to gSn_TX_BASE */ left_size = send_size – upper_size; memcpy(source_addr, gSn_TX_BASE, left_size); } else © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 50

    ... In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR Finished? / Socket Close If all the actions are finished, close the socket set CLOSE command */ Sn_CR = CLOSE; } © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 51

    ... IP raw IP Raw mode can be utilized if transport layer protocol of some ICMP or IGMP that W3150A+ does not support, needs to be processed. Socket Initialization It initializes the socket as IP raw. { START: /* sets IP raw mode */ Sn_MR = 0x03; /* sets Protocol value */ /* The value of Protocol is the value used in Protocol Field of IP Header. ...

  • Page 52

    ... Data Size (2) (*Data size except for 6 bytes of header) Send DATA? / Sending Process This is same as UDP. Refer to 5.2.2 UDP except that remote_port information is not needed. Complete Sending Timeout Finished? / Socket Closed Next actions are same as UDP. Refer to 5.2.2 UDP. © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 53

    ... In case of MAC raw, 2byte header is attached to the data received. The header structure is as below. Data Size (2) (*Data size include 2 bytes of header) Send DATA? / Sending Process This is same as UDP. Refer to 5.2.2 UDP except that remote_port information is not needed. © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 54

    ... Application Information For the communication with MCU, W3150A+ provides Direct and Indirect Bus I/F, and SPI I/F modes. For the communication with Ethernet PHY, MII is used. 6.1. Direct Bus I/F Mode. Direct Bus I/F mode uses 15bit address line and 8bit data line, /CS, /RD, /WR, /INT. 6.2. Indirect Bus I/F Mode. ...

  • Page 55

    ... Serial Peripheral Interface Mode uses only four pins for data communication. Four pins are SCLK, /SS, MOSI, MISO. W3150A+ uses one more pin for Enabling SPI Operation. This pin is SPI_EN pin. By asserting SPI_EN pin high, A[14~11] pins turn to SCLK, /SS, MOSI, MISO pins. Figure 6-1. Connection between MCU and W3150A+ © ...

  • Page 56

    ... Device Operation The W3150A+ is controlled by a set of instruntion that is sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with W3150A+ via the SPI bus which is composed of four signal lines: Slave Select(/SS), Serial Clock(SCLK), MOSI(Master Out Slave In), MISO(Master In Slave Out). ...

  • Page 57

    ... TX_CLK. When receiving data, in general, the Physical Layer Devices output CRS, RXDV, RXD[0:3], and COL signals in synchronization with the falling edges of RX_CLK, so the W3150A+ recognizes the signals at the rising edges of RX_CLK. © Copyright 2006 WIZnet Co., Inc. All rights reserved. ...

  • Page 58

    ... Input Current I 7.3. POWER DISSIPATION Symbol Parameter P Power consumption in 10BaseT 10Base P Power consumption in 100BaseT 100Base © Copyright 2006 WIZnet Co., Inc. All rights reserved. Rating -0.5 to 3.6 -0.5 to 5.5 (5V tolerant) ±5 - refer to qualification report in our website) -55 to 125 Test Condition Junction temperature is from -55°C to 125°C ...

  • Page 59

    ... AC Characteristics 7.4.1. Reset Timing Description 1. Reset Cycle Time 2. /RESET to internal PLOCK © Copyright 2006 WIZnet Co., Inc. All rights reserved. Min Max ...

  • Page 60

    ... Read Cycle Time 2. Valid Address to /CS low time 3. /CS low to /RD low time 4. /RD high to /CS high time 5. /RD low to Valid Data Output time 6. /RD high to Data High-Z Output time © Copyright 2006 WIZnet Co., Inc. All rights reserved. Min Max ...

  • Page 61

    ... Write Cycle Time 2. Valid Address to /CS low time 3. /CS low to /WR high time 4. /CS low to /WR low time 5. /WR high to /CS high time 6. /WR low to Valid Data time © Copyright 2006 WIZnet Co., Inc. All rights reserved. Min Max ...

  • Page 62

    ... SPI Timing Description 1 /SS low to SCLK high 2 Input setup time 3 Input hold time 4 Output setup time 5 Output hold time 6 SCLK time 7 SCLK high to /SS high © Copyright 2006 WIZnet Co., Inc. All rights reserved. Mode Min Max Slave 21 ns Slave 7 ns Slave ...

  • Page 63

    ... MII(Media Independent Interface) Timing MII Tx TIMING Description 1. TX_CLK to TXD, TX_EN 2. TXD, TX_EN setup time to TX_CLK 1. TX_CLK to TXD, TX_EN 2. TXD, TX_EN setup time to TX_CLK © Copyright 2006 WIZnet Co., Inc. All rights reserved. Notes Min 10 Mbps 202 ns 10 Mbps 195 ns 100 Mbps 22 ns ...

  • Page 64

    ... MII Rx TIMING Description 1. Valid Data to RX_CLK time (setup time) 2. RX_CLK to Valid Data time (hold time) 1. Valid Data to RX_CLK time (setup time) 2. RX_CLK to Valid Data time (hold time) © Copyright 2006 WIZnet Co., Inc. All rights reserved. Notes Min 10 Mbps Mbps 5 ns ...

  • Page 65

    ... Ramp up rate Pre-heat temperature at 175°C(±25°C) Temperature above 217°C Time within 5°C of actual peak temperature Peak temperature range Ramp-down rate © Copyright 2006 WIZnet Co., Inc. All rights reserved. < 3°C /second 77-95 seconds 96-107 seconds 17-25 seconds 258-260°C < 6°C /second ...

  • Page 66

    ... Package Description © Copyright 2006 WIZnet Co., Inc. All rights reserved ...

  • Page 67

    ... Copyright 2006 WIZnet Co., Inc. All rights reserved. ...