W3150A+ WIZnet, W3150A+ Datasheet - Page 22

• Manufacturer Part Number: W3150A+
• Description: Ethernet ICs ENET CONTR TCP/IP+MAC
• Manufacturer: WIZnet

Specifications of W3150A+

• Rohs: yes
• Product: Ethernet Transceivers
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 80 C
• Package / Case: LQFP-64
• Ethernet Connection Type: 10Base-T, 100Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IR (Interrupt Register) [R] [0x0015] [0x00]
This register is accessed by the host processor to know the cause of an interrupt.
Any interrupt can be masked in the Interrupt Mask Register (IMR). The /INT signal retain low as long as any
masked signal is set, and will not go high until all masked bits in this Register have been cleared.
*
Bit
CONFLICT
7
6
4
3
2
1
Difference from W3150A
5
7
CONFLICT
UNREACH
Reserved
Symbol
S3_INT
S2_INT
S1_INT
PPPoE
UNREACH
6
IP Conflict
It is set as ‘1’, when there is ARP request with same IP address as Source IP address.
This bit is cleared to ‘0’ by
Destination unreachable
W3150A+ will receive ICMP(Destination Unreachable) packet if not-existing destination
IP address is transmitted during UDP data transmission. (Refer to 5.2.2. UDP). In this
case, the IP address and the port number will be saved in Unreachable IP Address (UIPR)
and Unreachable Port Register (UPORT), and the bit will be set as ‘1’. This bit will be
cleared to ‘0’ by
PPPoE Close
In the PPPoE Mode, if the PPPoE connection is closed, ‘1’ is set. This bit will be cleared
to ‘0’ by
Reserved
Occurrence of Socket 3 Socket Interrupt
It is set in case that interrupt occurs at the socket 3. For more detailed information of
socket interrupt, refer to “Socket 3 Interrupt Register (S3_IR). This bit will be
automatically cleared when S3_IR is cleared to 0x00.
Occurrence of Socket 2 Socket Interrupt
It is set in case that interrupt occurs at the socket 2. For more detailed information of
socket interrupt, refer to “Socket 2 Interrupt Register(S2_IR). This bit will be
automatically cleared when S2_IR is cleared to 0x00.
Occurrence of Socket 1 Socket Interrupt
It is set in case that interrupt occurs at the socket 1. For more detailed information of
socket interrupt, refer to “Socket 1 Interrupt Register (S1_IR). This bit will be
automatically cleared when S1_IR is cleared to 0x00.
© Copyright 2006 WIZnet Co., Inc. All rights reserved.
writing ‘1’ to this bit.*
PPPoE
5
writing ‘1’ to this bit.*
Reserved
4
writing ‘1’ to this
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S3_INT
Description
3
bit.
*
S2_INT
2
S1_INT
1
S0_INT
0