W3150A+ WIZnet, W3150A+ Datasheet - Page 36

• Manufacturer Part Number: W3150A+
• Description: Ethernet ICs ENET CONTR TCP/IP+MAC
• Manufacturer: WIZnet

Specifications of W3150A+

• Rohs: yes
• Product: Ethernet Transceivers
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 80 C
• Package / Case: LQFP-64
• Ethernet Connection Type: 10Base-T, 100Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

5. Functional Description
By setting some register and memory operation, W3150A+ provides internet connectivity. This chapter
describes how it can be operated.
5.1. Initialization
Below register is for basic network configuration information to be configured according to the network
environment.
The Source Hardware Address Regiter (SHAR) is the H/W address to be used in MAC layer, and can be used
with the address that manufacturer has been assigned. The MAC address can be assigned from IEEE. For
more detail, refer to IEEE homepage.
This stage sets the socket tx/rx memory information. The base address and mask address of each socket
are fixed and saved in this stage.
In case of, assign 2K rx memory per socket.
{
}
RMSR = 0x55;
gS0_RX_BASE = chip_base_address + RX_memory_base_address(0x6000);
gS0_RX_MASK = 2K – 1 ;
gS1_RX_BASE = gS0_BASE + (gS0_MASK + 1);
gS1_RX_MASK = 2K – 1 ;
gS2_RX_BASE = gS1_BASE + (gS1_MASK + 1);
gS2_RX_MASK = 2K – 1 ;
gS3_RX_BASE = gS2_BASE + (gS2_MASK + 1);
gS3_RX_MASK = 2K – 1 ;
TMSR = 0x55;
Same
gS2_TX_MASK, gS3_TX_BASE and gS3_TX_MASK.
1. Gateway Address Register (GAR)
2. Source Hardware Address Register (SHAR)
3. Subnet Mask Register (SUBR)
4. Source IP Address Register (SIPR)
Setting network information
Set socket memory information
method,
// assign 2K rx memory per socket.
// assign 2K tx memory per socket.
set
© Copyright 2006 WIZnet Co., Inc. All rights reserved.
// 0x07FF, for getting offset address within assigned socket 0 RX memory.
gS0_TX_BASE,
gS0_TX_MASK,
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gS1_TX_BASE,
gS1_TX_MASK,
gS2_TX_BASE,