1893BFILFT IDT, 1893BFILFT Datasheet
1893BFILFT
Specifications of 1893BFILFT
Related parts for 1893BFILFT
1893BFILFT Summary of contents
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... Set Interface ICS1893BF, Rev. F, 5/13/10 IDT reserves the right to make changes in the device data identified in this publication without further notice. IDT advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ...
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... Functional Block: Media Independent Interface ..................................................... 32 6.2 Functional Block: Auto-Negotiation ........................................................................ 33 6.2.1 Auto-Negotiation General Process ........................................................................ 33 6.2.2 Auto-Negotiation: Parallel Detection ...................................................................... 34 6.2.3 Auto-Negotiation: Remote Fault Signaling ............................................................. 35 6.2.4 Auto-Negotiation: Reset and Restart ..................................................................... 35 6.2.5 Auto-Negotiation: Progress Monitor ....................................................................... 36 ICS1893BF, Rev. F, 5/13/10 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. 2 Table of Contents Page May, 2010 ...
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... Operation: Twisted-Pair Receiver ......................................................... 45 6.5.13 10Base-T Operation: Auto Polarity Correction ....................................................... 45 6.5.14 10Base-T Operation: Isolation Transformer ........................................................... 46 6.6 Functional Block: Management Interface ............................................................... 46 6.6.1 Management Register Set Summary ..................................................................... 46 6.6.2 Management Frame Structure ............................................................................... 46 ICS1893BF, Rev. F, 5/13/10 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. 3 Table of Contents Page May, 2010 ...
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... MF Preamble Suppression (bit 1.6) ....................................................................... 59 7.3.8 Auto-Negotiation Complete (bit 1.5) ....................................................................... 59 7.3.9 Remote Fault (bit 1.4) ............................................................................................ 60 7.3.10 Auto-Negotiation Ability (bit 1.3) ............................................................................ 60 7.3.11 Link Status (bit 1.2) ................................................................................................ 60 7.3.12 Jabber Detect (bit 1.1) ........................................................................................... 61 7.3.13 Extended Capability (bit 1.0) .................................................................................. 61 7.4 Register 2: PHY Identifier Register ........................................................................ 62 ICS1893BF, Rev. F, 5/13/10 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. 4 Table of Contents Page May, 2010 ...
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... Register 8: Auto-Negotiation Next Page Link Partner Ability Register ................... 74 7.10.1 Next Page (bit 8.15) ............................................................................................... 75 7.10.2 IEEE Reserved Bit (bit 8.14) .................................................................................. 75 7.10.3 Message Page (bit 8.13) ........................................................................................ 75 7.10.4 Acknowledge 2 (bit 8.12) ....................................................................................... 75 7.10.5 Message Code Field / Unformatted Code Field (bits 8.10:0) ................................. 75 ICS1893BF, Rev. F, 5/13/10 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. 5 Table of Contents Page May, 2010 ...
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... ICS Reserved (bits 18.13:6) ................................................................................... 85 7.13.4 Jabber Inhibit (bit 18.5) .......................................................................................... 85 7.13.5 ICS Reserved (bit 18.4) ......................................................................................... 85 7.13.6 Auto Polarity Inhibit (bit 18.3) ................................................................................. 85 7.13.7 SQE Test Inhibit (bit 18.2) ...................................................................................... 85 7.13.8 Link Loss Inhibit (bit 18.1) ...................................................................................... 86 7.13.9 Squelch Inhibit (bit 18.0) ........................................................................................ 86 ICS1893BF, Rev. F, 5/13/10 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. 6 Table of Contents Page May, 2010 ...
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... MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)................120 9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)..................121 9.5.13 100M MII Media Independent Interface: Receive Latency....................................122 ICS1893BF, Rev. F, 5/13/10 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. 7 Table of Contents Page May, 2010 ...
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... Jabber Timing .....................................................................................127 9.5.19 10Base-T: Normal Link Pulse Timing ..................................................................128 9.5.20 Auto-Negotiation Fast Link Pulse Timing .............................................................129 Chapter 10 Physical Dimensions of ICS1893BF Package........................................................... 130 Chapter 11 Ordering Information.................................................................................................... 132 ICS1893BF, Rev. F, 5/13/10 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. 8 Table of Contents Page May, 2010 ...
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... Page 132. Added “T” to the part ordering numbers to designate Tape and Reel packaging. • Rev D – Added top-side marking. • Rev E, 08/11/09 – Added “EOL” ordering information note per PDN U-09-01. • Rev F, 05/13/10 – Removed non-green parts per PDN U-09-01. ICS1893BF, Rev. F, 5/13/10 Copyright © 2009, IDT, Inc. All rights reserved. 9 Revision History May, 2010 ...
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... Min. minimum MLT-3 Multi-Level Transition Encoding (3 Levels) N/A Not Applicable NLP Normal Link Pulse No. Number NRZ Not Return to Zero NRZI Not Return to Zero, Invert on one ICS1893BF, Rev. F, 5/13/10 Chapter 1 Abbreviations and Acronyms Interpretation Copyright © 2009, IDT, Inc. All rights reserved. 10 May, 2010 ...
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... STA Station Management Entity STP shielded twisted pair TAF Technology Ability Field TP-PMD Twisted-Pair Physical Layer Medium Dependent Typ. typical UTP unshielded twisted pair ICS1893BF, Rev. F, 5/13/10 Chapter 1 Abbreviations and Acronyms Interpretation Copyright © 2009, IDT, Inc. All rights reserved. 11 May, 2010 ...
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... All numerical references to registers use decimal notation (and not hexadecimal). • When register name abbreviations are spelled out, words in parentheses indicate additional description that is not part of the register name abbreviation. Copyright © 2009, IDT, Inc. All rights reserved. 12 Chapter 2 Conventions and Nomenclature May, 2010 ...
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... In reference to the ICS1893BF, the term ‘Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). In reference to the ICS1893BF, the term ‘Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). Copyright © 2009, IDT, Inc. All rights reserved. 13 Chapter 2 Conventions and Nomenclature ...
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... PHY, which it translates and presents to its MAC Interface. Note: As per the ISO/IEC standard, the ICS1893BF does not affect, nor is it affected by, the underlying structure of the MAC frame it is conveying. ICS1893BF, Rev. F, 5/13/10 Chapter 3 Overview of the ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 14 May, 2010 ...
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... ICS1893BF signals and detects Normal Link Pulses. This action allows the integrity of the Link Segment with the remote link partner to be established and then reported to the ICS1893BF’s STA. ICS1893BF, Rev. F, 5/13/10 Chapter 3 Overview of the ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 15 May, 2010 ...
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... Section 4.4, “Auto-Negotiation Operations” • Section 4.5, “100Base-TX Operations” • Section 4.6, “10Base-T Operations” • Section 4.7, “Half-Duplex and Full-Duplex Operations” • Section 4.8, “Auto-MDI/MDIX Crossover” ICS1893BF, Rev. F, 5/13/10 Chapter 4 Operating Modes Overview Copyright © 2009, IDT, Inc. All rights reserved. 16 May, 2010 ...
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... As with the ICS189X products, the ICS1893BF reset design supports ‘hot insertion’ of its MII. (That is, the ICS1893BF can connect its MAC Interface to a MAC while power is already applied to the MAC.) ICS1893BF, Rev. F, 5/13/10 Chapter 4 Operating Modes Overview Operations”. 16.10:6)”.] Copyright © 2009, IDT, Inc. All rights reserved. 17 May, 2010 ...
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... Control Register bit 0.15 does not represent the status of a power-on reset. ICS1893BF, Rev. F, 5/13/10 Reset”. Section 4.1.1.2, “Exiting Power-Down”.] Section 9.5.15, “Reset: Power-On Copyright © 2009, IDT, Inc. All rights reserved. 18 Chapter 4 Operating Modes Overview Reset”. After the first Section 4.1.1.1, “Entering Reset” ...
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... Section 7.14, “Register 19: Extended Control Register 2” • Section 9.4, “DC Operating consumption while in the power-down state ICS1893BF, Rev. F, 5/13/10 16.10:6)”.] Characteristics”, which has tables that specify the ICS1893BF power Copyright © 2009, IDT, Inc. All rights reserved. 19 Chapter 4 Operating Modes Overview May, 2010 ...
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... When an STA sets the state of the ICS1893BF Extended Control Register 2, bit 19.1 to logic: • • Section 6.2, “Functional Block: Copyright © 2009, IDT, Inc. All rights reserved. 20 Chapter 4 Operating Modes Overview 100Base-TX Mode Zero, the 10Base-T modules always remain enabled, even during 100Base-TX operations ...
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... Section 7.2, “Register 0: Control Register” • Section 7.2.8, “Duplex Mode (bit 0.8)” • Section 7.3, “Register 1: Status Register” • Section 7.6, “Register 4: Auto-Negotiation Register” ICS1893BF, Rev. F, 5/13/10 Chapter 4 Operating Modes Overview Operations”. Copyright © 2009, IDT, Inc. All rights reserved. 21 May, 2010 ...
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... AMDIX_EN pin or by writing MDIO register 19 Bits 9:8 in the MDIO register. The Auto-MDI/MDIX function is independent of Auto-Negotiation and preceeds Auto-Negotiation when enabled. ICS1893BF, Rev. F, 5/13/10 Chapter 4 Operating Modes Overview Copyright © 2009, IDT, Inc. All rights reserved. 22 May, 2010 ...
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... Section 5.1, “MII Data Interface” • Section 5.2, “Serial Management Interface” • Section 5.3, “Twisted-Pair Interface” • Section 5.4, “Clock Reference Interface” • Section 5.5, “Status Interface” ICS1893BF, Rev. F, 5/13/10 Copyright © 2009, IDT, Inc. All rights reserved. 23 Chapter 5 Interface Overviews May, 2010 ...
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... TP_TXN) during a power-on reset. Upon completion of the reset process, the ICS1893BF enables its MII and enables its Twisted-Pair Transmit signals. ICS1893BF, Rev. F, 5/13/10 Insertion”, the ICS1893BF design allows hot insertion of its MII. That Copyright © 2009, IDT, Inc. All rights reserved. 24 Chapter 5 Interface Overviews ...
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... The transformer provides the isolation with one set of windings on one ground plane and another set of windings on the second ground plane. 5.3.1 Twisted-Pair Transmitter The twisted-pair transmitter driver uses an H-bridge configuration. IDT transformer requirements: • Turns Ratio 1:1 • Chokes may be used on chip or cable side or both sides • ...
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... Tap 120 nH 3PF 61.9Ω 50Ω. 0.1 µF o 61.9Ω 1% Center Tap 120 nH 3PF 61.9Ω 1% 0.1 µF = 50Ω. o Copyright © 2009, IDT, Inc. All rights reserved. 26 Chapter 5 Interface Overviews Chassis Ground Plane Separate Ground Plane To RJ-45 75Ω To RJ-45 75Ω 0.1 µF Chassis GND May, 2010 ...
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... Table 5.2. Figure 5-2. Crystal or Oscillator Operation Crystal REF_OUT Oscillator REF_OUT 46 NC CMOS 25.000 MHz ICS1893BF, Rev. F, 5/13/10 ICS1893BF REF_IN 47 25.000MHz 33 pF ICS1893BF REF_IN 47 33 Ohm 10 pF Copyright © 2009, IDT, Inc. All rights reserved. 27 Chapter 5 Interface Overviews May, 2010 ...
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... ICS1893BF, Rev. F, 5/13/10 Symbol Minimum Typical Maximum F0 24.99875 25.00000 ∆ F/f Cin 3 Symbol Minimum Typical Maximum F0 24.99875 25.00000 ∆ F/f Tw/T 35 2.79 Tjitter CIN 3 Copyright © 2009, IDT, Inc. All rights reserved. 28 Chapter 5 Interface Overviews Unit 25.00125 MHz ± 50 ppm pF Unit 25.00125 MHz ± 50 ppm 65 % Volts 0.33 ...
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... Adding 10KΩ resistors across the LEDs ensures the PHY address is fully defined during slow VDD power-ramp conditions. 6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII tri-stated.) ICS1893BF, Rev. F, 5/13/10 Copyright © 2009, IDT, Inc. All rights reserved. 29 Chapter 5 Interface Overviews May, 2010 ...
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... For more reliable address capture during power-on reset, add a 10KΩ resistor across the LED. ICS1893BF, Rev. F, 5/13/10 ICS1893BF P2LI 4 LINK TRANS LED 10KΩ LED 1KΩ Copyright © 2009, IDT, Inc. All rights reserved. 30 Chapter 5 Interface Overviews P1CL P0AC 3 1 ACTIVITY COL VDD 1KΩ ...
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... Section 6.3, “Functional Block: 100Base-X PCS and PMA Sublayers” • Section 6.4, “Functional Block: 100Base-TX TP-PMD Operations” • Section 6.5, “Functional Block: 10Base-T Operations” • Section 6.6, “Functional Block: Management Interface” ICS1893BF, Rev. F, 5/13/10 Copyright © 2009, IDT, Inc. All rights reserved. 31 Chapter 6 Functional Blocks May, 2010 ...
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... QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with a single register access. ICS1893BF, Rev. F, 5/13/10 Chapter 7, “Management Register Copyright © 2009, IDT, Inc. All rights reserved. 32 Chapter 6 Functional Blocks Set”) consists ...
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... ICS1893BF does not support this technology.) (3) 100Base-TX (half duplex) (4) 10Base-T full duplex (5) 10Base-T (half duplex) ICS1893BF, Rev. F, 5/13/10 Section 4.4, “Auto-Negotiation Copyright © 2009, IDT, Inc. All rights reserved. 33 Chapter 6 Functional Blocks Operations”.) May, 2010 ...
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... Another possibility is that the ICS1893BF senses that it is receiving multiple technology indications. In this situation, the ICS1893BF cannot determine which technology to enable. It informs the STA of this problem by setting to logic one the Auto-Negotiation Expansion Register’s Parallel Detection Fault bit (bit 6.4). ICS1893BF, Rev. F, 5/13/10 Copyright © 2009, IDT, Inc. All rights reserved. 34 Chapter 6 Functional Blocks ...
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... Toggling the Control Register’s Auto-Negotiation Enable bit (bit 0.12) from a logic one to a logic zero, and back to a logic one. ICS1893BF, Rev. F, 5/13/10 and Section 7.3.9, “Remote Fault (bit Section 6.2.5, “Auto-Negotiation: Copyright © 2009, IDT, Inc. All rights reserved. 35 Chapter 6 Functional Blocks 1.4)”. May, 2010 ...
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... Physical Medium Dependent sublayer. Functionally, the PMA sublayer is responsible for the following: • Link Monitoring • Carrier Detection • NRZI encoding/decoding • Transmit Clock Synthesis • Receive Clock Recovery ICS1893BF, Rev. F, 5/13/10 Copyright © 2009, IDT, Inc. All rights reserved. 36 Chapter 6 Functional Blocks May, 2010 ...
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... Receive and Data States. It continues this process until detecting one of the following: • An End-of-Stream Delimiter (ESD, that is, the /T/R/ symbols) • An error • A premature end (IDLEs) ICS1893BF, Rev. F, 5/13/10 Copyright © 2009, IDT, Inc. All rights reserved. 37 Chapter 6 Functional Blocks May, 2010 ...
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... Can confirm the /I/J/K/ symbols, then the Receive state machine transitions to the ‘Receive’ state. The COL control signal is generated by the transmit modules. For details, see Transmit Module”. ICS1893BF, Rev. F, 5/13/10 and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 38 Chapter 6 Functional Blocks Section Bits”.) Section 6.3.3.1, “PCS ...
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... The MAC Interface bypasses the stream cipher scrambler/descrambler when in the 100M Symbol Interface mode. ICS1893BF, Rev. F, 5/13/10 16.2)”. Section 4.5, “100Base-TX Section 5.3, “Twisted-Pair Table 7-16, which minimizes crosstalk and noise in repeater applications. Copyright © 2009, IDT, Inc. All rights reserved. 39 Chapter 6 Functional Blocks Section 7.11.7, “Invalid Operations”. Interface”. May, 2010 ...
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... In reference to the ICS1893BF, the term ‘Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). 2. For information on the 10Base-T Twisted-Pair Transmitter, see Twisted-Pair Transmitter”. ICS1893BF, Rev. F, 5/13/10 Section 6.5.11, “10Base-T Operation: Copyright © 2009, IDT, Inc. All rights reserved. 40 Chapter 6 Functional Blocks May, 2010 ...
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... The 10Base-T and 100Base-TX operations differ as follows. 10Base-T operations are fundamentally simpler than 100Base-TX operations. The data rate is slower, requiring less encoding than 100Base-TX operations. In addition, the bandwidth requirements (and therefore the line attenuation issues) are not as severe as with 100-MHz operations. Consequently, when an ICS1893BF is set for 10Base-T operations, it requires fewer internal circuits in contrast to 100Base-TX operations ...
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... The criteria used by the Link Monitor Function to declare a link either valid or invalid depends upon these factors: the present state of the link, whether its Smart Squelch function is enabled, and the incoming data. ICS1893BF, Rev. F, 5/13/10 and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 42 Chapter 6 Functional Blocks Bits”.) ...
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... In 10Base-T mode, an ICS1893BF appends an IDL to the end of each packet during data transmission. The receiving PHY (the remote link partner) sees this IDL and removes it from the data stream. ICS1893BF, Rev. F, 5/13/10 Copyright © 2009, IDT, Inc. All rights reserved. 43 Chapter 6 Functional Blocks ...
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... ICS1893BF executes its SQE Test, it asserts the COL signal to its MAC Interface for a pre-determined time duration (ISO/IEC specified). [For more information, see (SQE)”.] ICS1893BF, Rev. F, 5/13/10 Bits”.) Section 9.5.17, “10Base-T: Heartbeat Timing Copyright © 2009, IDT, Inc. All rights reserved. 44 Chapter 6 Functional Blocks Section 9.5.18, Section 7.1.4.1, “Latching High ...
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... Zero, the ICS1893BF automatically senses and corrects a reversed or inverted signal polarity on its Twisted-Pair Receive pins (TP_RXP and TP_RXN). • One, the ICS1893BF disables this feature. ICS1893BF, Rev. F, 5/13/10 (SQE)”. Receiver”. Copyright © 2009, IDT, Inc. All rights reserved. 45 Chapter 6 Functional Blocks Section Transmitter”. May, 2010 ...
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... Section 7.1.4.2, “Latching Low Transformer”. Summary”) Structure”) Chapter 7, “Management Register Table 6-1 summarizes the Management Frame Copyright © 2009, IDT, Inc. All rights reserved. 46 Chapter 6 Functional Blocks Bits”.) Section 6.4.7, Set”) includes the mandatory ‘Basic’ May, 2010 ...
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... An STA uniquely identifies each of the PHYs that share a single serial management interface by using this 5-bit PHY Address field, PHYAD. ICS1893BF, Rev. F, 5/13/10 Data 11..11 01 10/01 (read/write) AAAAA RRRRR Z0/10 (read/write) DDD..DD Section 7.1.2, “Management Register Bit Copyright © 2009, IDT, Inc. All rights reserved. 47 Chapter 6 Functional Blocks Comment 32 ones 2 bits 2 bits 5 bits 5 bits 2 bits 16 bits Access” ...
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... Write, an ICS1893BF waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin. 6.6.2.8 Management Frame Data A valid management frame includes a 16-bit Data field for exchanging the register contents between the ICS1893BF and the STA. All Management Registers are 16 bits wide, matching the width of the Data field. During a transaction that is a: • ...
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... Section 7.11, “Register 16: Extended Control Register” • Section 7.12, “Register 17: Quick Poll Detailed Status Register” • Section 7.13, “Register 18: 10Base-T Operations Register” • Section 7.14, “Register 19: Extended Control Register 2” ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set Copyright © 2009, IDT, Inc. All rights reserved. 49 May, 2010 ...
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... Reserved by IEEE 16 through 31 Vendor-Specific (IDT) Registers Table 7-2 lists the IDT-specific registers that the ICS1893BF implements. These registers enhance the performance of the ICS1893BF and provide the Station Management entity (STA) with additional control and status capabilities. Table 7-2. IDT-Specific Registers Register Address ...
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... Section 5.5, “Status Interface” • Section 7.11, “Register 16: Extended Control Register” • Section 8.2.2, “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins” Copyright © 2009, IDT, Inc. All rights reserved. 51 Chapter 7 Management Register Set Description Table 7-4 lists the valid default values for ...
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... When the STA writes a logic one bit, the ICS1893BF begins executing the function assigned to that bit. After the ICS1893BF completes executing the function, it clears the bit to indicate that the action is complete. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set Copyright © 2009, IDT, Inc. All rights reserved. 52 May, 2010 ...
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... Restart Auto-Negotiation Half-duplex operation Full-duplex operation No effect Enable collision test Always 0 N/A Always 0 N/A Always 0 N/A Always 0 N/A Always 0 N/A Always 0 N/A Always 0 N/A Table 7-16: Copyright © 2009, IDT, Inc. All rights reserved. 53 Chapter 7 Management Register Set Chapter 1, “Abbreviations and Acronyms”. Ac- SF De- cess fault R R/W – 0 R/W – 1 R/W – ...
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... The ICS1893BF bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data rate and the duplex mode. – One: • The ICS1893BF enables the Auto-Negotiation sublayer. • The ICS1893BF isolates bit 0.13 and bit 0.8. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set Copyright © 2009, IDT, Inc. All rights reserved. 54 May, 2010 ...
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... ICS1893BF automatically sets this bit to logic zero, thereby providing the self-clearing feature. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set and Section 7.1.4.2, “Latching Low Table 7-16. If the PHY address: Copyright © 2009, IDT, Inc. All rights reserved. 55 Section Bits”.) May, 2010 ...
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... ICS1893BF, an STA must maintain the default value of these bits. Therefore, ICS recommends that during any STA write operation, an STA write the default value to all reserved bits, even those bits that are Read Only. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set Copyright © 2009, IDT, Inc. All rights reserved. 56 May, 2010 ...
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... Remote fault detected N/A Always 1: PHY has Auto-Negotiation ability Link is invalid/down Link is valid/established No jabber condition Jabber condition detected N/A Always 1: PHY has extended capabilities Copyright © 2009, IDT, Inc. All rights reserved. 57 Chapter 7 Management Register Set Acronyms”. Ac- SF De- Hex cess fault RO – ...
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... Command Override Write Enable bit, in Section 7.11, “Register 16: Extended Control ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set Section 7.11, “Register 16: Extended Register”.] Copyright © 2009, IDT, Inc. All rights reserved. 58 Section 7.11, “Register 16: Section 7.11, “Register 16: May, 2010 ...
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... An Auto-Negotiation Restart does not clear an LH bit. However, performing two consecutive reads of this register provides the present state of the bit. ICS1893BF, Rev. F, 5/13/10 Section 7.11, “Register 16: Extended Control and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 59 Chapter 7 Management Register Set Register”.] Section 6.2, “Functional Block: Bits” ...
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... For more information on the Link Monitor Function (relative to the Link Status bit), see “10Base-T Operation: Link ICS1893BF, Rev. F, 5/13/10 and Section 7.1.4.2, “Latching Low Section 7.1.4.1, “Latching High Bits” Monitor”. Copyright © 2009, IDT, Inc. All rights reserved. 60 Chapter 7 Management Register Set Bits”.) and Section 7.1.4.2, “Latching Low Section 6 ...
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... The STA reads bit 1.0 to determine if the ICS1893BF has an extended register set. In the ICS1893BF this bit is always logic one, indicating that it has extended registers. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 61 Bits”.) May, 2010 ...
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... CW N/A N/A CW N/A N/A CW N/A N/A CW N/A N/A CW N/A N/A CW N/A N/A CW N/A N/A CW N/A N/A CW N/A N/A CW N/A N/A CW N/A N/A CW Copyright © 2009, IDT, Inc. All rights reserved. 62 Chapter 7 Management Register Set Chapter 1, “Abbreviations and Acronyms”. Special Default Hex Function – – 0 – 0 – 0 – – 0 – 0 – 0 – – 0 – ...
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... Register 2 Section 7.4, “Register 2: PHY Identifier Table 7-5, see When Bit = 0 When Bit = 1 N/A N/A N/A N/A Copyright © 2009, IDT, Inc. All rights reserved. 63 Chapter 7 Management Register Set provides the ISO/IEC-defined mapping Third Octet ...
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... ICS1893BF, Rev. F, 5/13/10 When Bit = 0 When Bit = 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Description IDT 1893B Release with Auto-MDIX Copyright © 2009, IDT, Inc. All rights reserved. 64 Chapter 7 Management Register Set Access Special Default Hex Function CW – – – – – – – ...
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... Do not advertise ability Advertise ability IEEE 802.3-specified default N/A IEEE 802.3-specified default N/A IEEE 802.3-specified default N/A IEEE 802.3-specified default N/A N/A IEEE 802.3-specified default Copyright © 2009, IDT, Inc. All rights reserved. 65 Chapter 7 Management Register Set Acronyms”. Ac- SF De- Hex ...
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... ICS1893BF, an STA must maintain the default value of these bits. Therefore, ICS recommends that during any STA write operation, an STA write the default value to all reserved bits, even those bits that are Read Only. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set Copyright © 2009, IDT, Inc. All rights reserved. 66 May, 2010 ...
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... These bits indicate to the remote link partner the type of message being sent during the auto-negotiation process. The ICS1893BF supports IEEE Std. 802.3, represented by a value of 00001b in bits 4.4:0. The ISO/IEC 8802-3 standard defines the Selector Field technologies in Annex 28A. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set Copyright © 2009, IDT, Inc. All rights reserved. 67 May, 2010 ...
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... Link partner is capable IEEE 802.3 defined. Always 0. N/A IEEE 802.3 defined. Always 0. N/A IEEE 802.3 defined. Always 0. N/A IEEE 802.3 defined. Always 0. N/A N/A IEEE 802.3 defined. Always 1. Copyright © 2009, IDT, Inc. All rights reserved. 68 Chapter 7 Management Register Set Acronyms”. When Bit = 1 Ac- SF De- ...
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... Written STA, the STA must use the default value specified in this data sheet. IDT uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893BF, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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... Writes to a reserved bit, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893BF, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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... Receives valid FLP bursts from its remote link partner (thereby indicating that it can participate in the auto-negotiation process), then the ICS1893BF sets this bit to a logic one. ICS1893BF, Rev. F, 5/13/10 and Section 7.1.4.2, “Latching Low and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 71 Chapter 7 Management Register Set Bits”.) Bits”.) May, 2010 ...
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... Bit value depends on Bit value depends on the particular message the particular message Bit value depends on Bit value depends on the particular message the particular message Copyright © 2009, IDT, Inc. All rights reserved. 72 Chapter 7 Management Register Set Acronyms”. Ac- SF De- Hex ...
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... Written STA, the STA must use the default value specified in this data sheet. IDT uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893BF, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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... Bit value depends on Bit value depends on the particular message the particular message Bit value depends on Bit value depends on the particular message the particular message Copyright © 2009, IDT, Inc. All rights reserved. 74 Chapter 7 Management Register Set Acronyms”. Ac- SF De- Hex ...
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... Written STA, the STA must use the default value specified in this data sheet. IDT uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893BF, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
Page 76
... Interface”. Test mode Read unspecified Read unspecified NRZ encoding NRZI encoding Disabled Enabled Read unspecified Read unspecified Stream Cipher enabled Stream Cipher disabled Copyright © 2009, IDT, Inc. All rights reserved. 76 Chapter 7 Management Register Set Acronyms”. Ac- SF De- Hex cess fault ...
Page 77
... Written STA, the STA must use the default value specified in this data sheet. IDT uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893BF, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
Page 78
... Copyright © 2009, IDT, Inc. All rights reserved. 78 Chapter 7 Management Register Set May, 2010 ...
Page 79
... Auto-Negotiation process complete Signal present No signal present No jabber detected Jabber detected No remote fault detected Remote fault detected Link is not valid Link is valid Copyright © 2009, IDT, Inc. All rights reserved. 79 Chapter 7 Management Register Set Acronyms”. Bits”.) Ac- SF De- Hex cess ...
Page 80
... Machine achieves. That is, they are updated only if the binary value of the next state is greater than the binary value of the present state as outlined in ICS1893BF, Rev. F, 5/13/10 Operations”) Section 7.2.4, “Auto-Negotiation Enable (bit Section 7.2.7, “Restart Auto-Negotiation (bit Table 7-19. Copyright © 2009, IDT, Inc. All rights reserved. 80 Chapter 7 Management Register Set 0.12)”] 0.9)”] May, 2010 ...
Page 81
... Section 7.1.4.2, “Latching Low and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 81 Chapter 7 Management Register Set Auto- Auto- Negotiation Negotiation Monitor Bit 1 Monitor Bit 0 (Bit 17.12) (Bit 17.11 ...
Page 82
... Note: This bit has no definition in 10Base-T mode. ICS1893BF, Rev. F, 5/13/10 and Section 7.1.4.2, “Latching Low and Section 7.1.4.2, “Latching Low and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 82 Chapter 7 Management Register Set Section Bits”.) Section Bits”.) Section Bits”.) ...
Page 83
... This bit is a 10Base-T function. 7.12.13 Remote Fault (bit 17.1) Bit 17.1 is functionally identical to bit 1.4. 7.12.14 Link Status (bit 17.0) Bit 17.0 is functionally identical to bit 1.2. ICS1893BF, Rev. F, 5/13/10 and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 83 Chapter 7 Management Register Set Section Bits”.) May, 2010 ...
Page 84
... Normal SQE test behavior SQE test disabled Normal Link Loss behavior Link Always = Link Pass Normal squelch behavior No squelch and Section 7.1.4.2, “Latching Low Copyright © 2009, IDT, Inc. All rights reserved. 84 Chapter 7 Management Register Set Acronyms”. Ac- SF De- cess ...
Page 85
... This bit is a control bit and not a status bit. Therefore not updated to indicate this automatic inhibiting of the SQE test in full-duplex mode or repeater mode. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set 16.14:11)”, the text for which also applies here. 16.14:11)”, the text for which also applies here. Copyright © 2009, IDT, Inc. All rights reserved. 85 May, 2010 ...
Page 86
... Zero, before the ICS1893BF can establish a valid link, the ICS1893BF must receive valid 10Base-T data. • One, before the ICS1893BF can establish a valid link, the ICS1893BF must receive both valid 10Base-T data followed by an IDL. ICS1893BF, Rev. F, 5/13/10 Chapter 7 Management Register Set Copyright © 2009, IDT, Inc. All rights reserved. 86 May, 2010 ...
Page 87
... Read unspecified Read unspecified Read unspecified Read unspecified Read unspecified Read unspecified Read unspecified Read unspecified Do not automatically Power down power down automatically Copyright © 2009, IDT, Inc. All rights reserved. 87 Chapter 7 Management Register Set Acronyms”. Ac- SF De- Hex cess fault RO – ...
Page 88
... Table 7-22. AMDIX_EN (Pin 10) and Control Bits 19. 9:8 AMDIX_EN (Pin 10 ICS1893BF, Rev. F, 5/13/10 16.14:11)”, the text for which also applies here. AMDIX_EN MDI_MODE [Reg 19:9] [Reg 19: Copyright © 2009, IDT, Inc. All rights reserved. 88 Chapter 7 Management Register Set Tx/Rx MDI Configuration straight cross straight May, 2010 ...
Page 89
... ICS1893BF, Rev. F, 5/13/10 AMDIX_EN MDI_MODE [Reg 19:9] [Reg 19: MDIO register 13h bit 9 16.14:11)”, the text for which also applies here. Copyright © 2009, IDT, Inc. All rights reserved. 89 Chapter 7 Management Register Set Tx/Rx MDI Configuration x straight / cross (auto selected) 0 ...
Page 90
... ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 90 VDD REF_IN REF_OUT VDD CRS COL TXD3 TXD2 TXD1 TXD0 TXEN TXCLK VSS RXER RXCLK VDD RXDV RXD0 RXD1 RXD2 RXD3 ...
Page 91
... Bit 0 of PHY Address, PHYAD[0], OR Activity LED Pin No. Signal Description 9 Output Indication, High=100baseTX Operation 10 Auto-MDIX Enable (built-in internal 50K Ohm pull-up) 20 100M Transmit Current Set Resistors 19 10M Transmit Current Set Resistor Copyright © 2009, IDT, Inc. All rights reserved. 91 May, 2010 ...
Page 92
... Frequency Reference Input: 25 MHz Input Clock or Crystal 46 Frequency Reference Output for Crystal 23 System Reset (active low) Signal Description Twisted Pair A Positive Twisted Pair A Negative Twisted Pair B Positive Twisted Pair B Negative Table 8-5 must not float. Copyright © 2009, IDT, Inc. All rights reserved. 92 May, 2010 ...
Page 93
... The ICS1893BF asserts its Collision LED for a period of approximately 70 msec when it detects a collision. Caution: This pin must not float. (See the notes at “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins”.) Copyright © 2009, IDT, Inc. All rights reserved. 93 Section 5.5, “Status Interface”. Section 8.2.2, Section 5.5, “ ...
Page 94
... Asserted, this state indicates the ICS1893BF has Transmit activity. Caution: This pin must not float. (See the notes at “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins”.) Copyright © 2009, IDT, Inc. All rights reserved. 94 Section 5.5, “Status Interface”. Section 8.2.2, Section 5.5, “ ...
Page 95
... Asserted, this state indicates the ICS1893BF has Receive activity. Caution: This pin must not float. (See the notes at “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins”.) Copyright © 2009, IDT, Inc. All rights reserved. 95 Section 5.5, “Status Interface”. Section 8.2.2, ...
Page 96
... For more information on hardware resets, see the following: – Section 4.1.2.1, “Hardware Reset” – Section 9.5.16, “Reset: Hardware Reset and Power-Down” Copyright © 2009, IDT, Inc. All rights reserved. 96 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Description Section 9.3, Values”. ...
Page 97
... The ICS1893BF uses the signal on the MDC pin to synchronize the transfer of management information between the ICS1893BF and the Station Management Entity (STA), using the serial MDIO data line. The MDC signal is sourced by the STA. Copyright © 2009, IDT, Inc. All rights reserved. 97 May, 2010 ...
Page 98
... The RXCLK aligns once per packet. Note: The signal on the RXCLK pin is conditioned by the RXTRI pin. Copyright © 2009, IDT, Inc. All rights reserved. 98 100Base-TX The RXCLK frequency is 25 MHz. The ICS1893BF generates its ...
Page 99
... The ICS1893BF generates this clock signal to synchronize the transfer of data from the MAC Interface to the ICS1893BF. When the mode is: • 10Base-T, the TXCLK frequency is 2.5 MHz. • 100Base-TX, the TXCLK frequency is 25 MHz. Copyright © 2009, IDT, Inc. All rights reserved. 99 Chapter 9.5.6, May, 2010 ...
Page 100
... TXD[3:0] synchronously with TXCLK. The ICS1893BF then transmits this data over the media. • Following the de-assertion of TXEN, the ICS1893BF terminates transmission of nibbles over the media. Copyright © 2009, IDT, Inc. All rights reserved. 100 May, 2010 ...
Page 101
... VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS ICS1893BF, Rev. F, 5/13/10 Chapter 8 Pin Diagram, Listings, and Descriptions Pin No. Signal Description Power 7 3.3V 14 3.3V 18 3.3V 22 3.3V 24 3.3V 33 3.3V 45 3.3V 48 3.3V Ground Copyright © 2009, IDT, Inc. All rights reserved. 101 May, 2010 ...
Page 102
... TP_AN 5 VDD 6 VDD 7 TP_BN 8 TP_BP 9 VSS 10 VDD_A 11 10TCSR 12 100TCSR 13 VSS 14 ICS1893BF, Rev. F, 5/13/10 Chapter 8 Pin Diagram, Listings, and Descriptions ICS1893BK 8x8 56L MLF2 Copyright © 2009, IDT, Inc. All rights reserved. 102 42 TXD3 41 TXD2 40 TXD1 39 TXD0 38 TXEN 37 TXCLK 36 VSS 35 RXER 34 RXCLK 33 VDD 32 ...
Page 103
... PHYAD[1] / Collision LED 49 PHYAD[0] / Activity LED Pin No. Signals Description 1 Output Speed indication, High=100baseTX 2 Auto-MDIX Enable (built-in internal 50K Ohm pull-up) 12 10M Transmit Amplitude Current Set Resistor 13 100M Transmit Amplitude Current Set Resistor Copyright © 2009, IDT, Inc. All rights reserved. 103 May, 2010 ...
Page 104
... Frequency Ref Input: 25MHz Clock or Crystal 46 Frequency Ref Output for Crystal 17 System Reset (active low) Pin No. Signals Description 4 Twisted Pair A Positive 5 Twisted Pair A Negative 9 Twisted Pair B Positive 8 Twisted Pair B Negative Copyright © 2009, IDT, Inc. All rights reserved. 104 May, 2010 ...
Page 105
... Chapter 8 Pin Diagram, Listings, and Descriptions Pin No. Signals Description 6 Power 3.3V 7 Power 3.3V 11 Power 3.3V 15 Power 3.3V 23 Power 3.3V 33 Power 3.3V 45 Power 3.3V 48 Power 3.3V 55 Power 3.3V 3 Ground 10 Ground 14 Ground 16 Ground 18 Ground 19 Ground 20 Ground 21 Ground 22 Ground 24 Ground 25 Ground 36 Ground 50 Ground 53 Ground Copyright © 2009, IDT, Inc. All rights reserved. 105 May, 2010 ...
Page 106
... Table 9-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893BF. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the ICS1893BF at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...
Page 107
... See Figure 9-1 510 1k ICS1893BF 10TCSR 19 12.1 KΩ 1% 10TCSR 100TCSR 1.54KΩ 1% Copyright © 2009, IDT, Inc. All rights reserved. 107 Chapter 9 DC and AC Operating Conditions Tolerance Units – ± 50 ppm † MHz – 1% – 1% 10k – 100TCSR ...
Page 108
... IDD Symbol Conditions V VDD_IO = 3. VDD_IO = 3. VDD_IO = 3. VDD_IO = 3. VDD_IO = 3. VDD_IO = 3. Copyright © 2009, IDT, Inc. All rights reserved. 108 Chapter 9 DC and AC Operating Conditions Min. Typ. Max. Units – – 110 125 mA – – ...
Page 109
... MII Output Drive Impedance ICS1893BF, Rev. F, 5/13/10 Symbol Test Conditions V VDD_IO = 3. VDD_IO = 3. Conditions Minimum – – – – VDD_IO = 3.3V – Copyright © 2009, IDT, Inc. All rights reserved. 109 Chapter 9 DC and AC Operating Conditions Min. Max. Units 2.97 – V – 0.33 V Typical Maximum Units – – ...
Page 110
... Time Parameter Period t1 REF_IN Duty Cycle t2 REF_IN Period Figure 9-2. REF_IN Timing Diagram REF_IN ICS1893BF, Rev. F, 5/13/10 Chapter 9 DC and AC Operating Conditions Conditions – – Copyright © 2009, IDT, Inc. All rights reserved. 110 Figure 9-2 Min. Typ. Max. Units – 40 – ns ...
Page 111
... TXCLK Period Figure 9-3. Transmit Clock Timing Diagram TXCLK ICS1893BF, Rev. F, 5/13/10 Chapter 9 DC and AC Operating Conditions Conditions – 100M MII (100Base-TX) 10M MII (10Base-T) t1 t2x Copyright © 2009, IDT, Inc. All rights reserved. 111 Min. Typ. Max. Units – 40 – ...
Page 112
... RXCLK Period t2b RXCLK Period Figure 9-4. Receive Clock Timing Diagram t1 RXCLK ICS1893BF, Rev. F, 5/13/10 Conditions – 100M MII (100Base-TX) 10M MII (10Base-T) t2 Copyright © 2009, IDT, Inc. All rights reserved. 112 Chapter 9 DC and AC Operating Conditions Min. Typ. Max – 40 – – ...
Page 113
... TXD[3:0], TXEN, TXER Hold after TXCLK Rise Figure 9-5. 100M MII / 100M Stream Interface Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER ICS1893BF, Rev. F, 5/13/10 Parameter Conditions t1 t2 Copyright © 2009, IDT, Inc. All rights reserved. 113 Chapter 9 DC and AC Operating Conditions Min. Typ. Max. – 15 – – ...
Page 114
... TXD[3:0], TXEN, TXER Hold after TXCLK Rise Figure 9-6. 10M MII Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER ICS1893BF, Rev. F, 5/13/10 Parameter Conditions t1 t2 Copyright © 2009, IDT, Inc. All rights reserved. 114 Chapter 9 DC and AC Operating Conditions Min. Typ. Max. – 375 – – ...
Page 115
... RXD[3:0], RXDV, and RXER Hold after RXCLK Rise Figure 9-7. MII Interface Synchronous Receive Timing Diagram RXCLK RXD[3:0] RXDV RXER ICS1893BF, Rev. F, 5/13/10 Chapter 9 DC and AC Operating Conditions Parameter t1 t2 Copyright © 2009, IDT, Inc. All rights reserved. 115 Min. Typ. Max. Units 10.0 – – ns 10.0 – ...
Page 116
... MDC MDIO (Input) ICS1893BF, Rev. F, 5/13/10 Figure 9-8 shows the timing diagram for the time periods. Parameter Copyright © 2009, IDT, Inc. All rights reserved. 116 Chapter 9 DC and AC Operating Conditions Conditions Min. Typ. Max. – 160 – – – ...
Page 117
... Figure 9-9. 10M MII Receive Latency Timing Diagram † TP_RX RXCLK RXD 5 † Manchester encoding is not shown. ICS1893BF, Rev. F, 5/13/10 Parameter Conditions 10M MII 5 t1 Copyright © 2009, IDT, Inc. All rights reserved. 117 Chapter 9 DC and AC Operating Conditions Min. Typ. Max. Units – 6.5 7 Bit times 5 May, 2010 D ...
Page 118
... Figure 9-10. 10M MII Transmit Latency Timing Diagram TXEN TXCLK TXD † TP_TX † Manchester encoding is not shown. ICS1893BF, Rev. F, 5/13/10 Parameter Conditions 10M MII Copyright © 2009, IDT, Inc. All rights reserved. 118 Chapter 9 DC and AC Operating Conditions Min. Typ. Max. Units – 1.2 2 Bit times 5 May, 2010 ...
Page 119
... Figure 9-11. MII / 100M Stream Interface Transmit Latency Timing Diagram TXEN TXCLK TXD Preamble /J/ † TP_TX † Shown unscrambled. ICS1893BF, Rev. F, 5/13/10 Chapter 9 DC and AC Operating Conditions Conditions MII mode Preamble /K/ t1 Copyright © 2009, IDT, Inc. All rights reserved. 119 Min. Typ. Max. Units – 2.8 3 Bit times May, 2010 ...
Page 120
... TXEN De-Asserted to CRS De-Asserted Figure 9-12. 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) TXEN TXCLK CRS t1 ICS1893BF, Rev. F, 5/13/10 Parameter t2 Copyright © 2009, IDT, Inc. All rights reserved. 120 Chapter 9 DC and AC Operating Conditions Condi- Min. Typ. Max. Units tions ...
Page 121
... TXEN De-Asserted to CRS De-Asserted Figure 9-13. 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) TXEN TXCLK CRS t1 ICS1893BF, Rev. F, 5/13/10 Parameter t2 Copyright © 2009, IDT, Inc. All rights reserved. 121 Chapter 9 DC and AC Operating Conditions Condi- Min. Typ. Max. Units tions 0 – ...
Page 122
... Figure 9-14. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram † TP_RX RXCLK RXD † Shown unscrambled. ICS1893BF, Rev. F, 5/13/10 Chapter 9 DC and AC Operating Conditions Conditions t1 Copyright © 2009, IDT, Inc. All rights reserved. 122 Min. Typ. Max. Units – Bit times May, 2010 ...
Page 123
... First bit † TP_RX CRS COL t2 † Shown unscrambled. ICS1893BF, Rev. F, 5/13/10 Parameter Conditions Half-Duplex Mode Half-Duplex Mode t1 Copyright © 2009, IDT, Inc. All rights reserved. 123 Chapter 9 DC and AC Operating Conditions Min. Typ. Max. – 10 – 14 Bit times 9 – 13 Bit times – ...
Page 124
... Period VDD ≥ 2 Reset Complete t1 Figure 9-16. Power-On Reset Timing Diagram 2.7 V VDD TXCLK Valid ICS1893BF, Rev. F, 5/13/10 Parameter Conditions t1 Copyright © 2009, IDT, Inc. All rights reserved. 124 Chapter 9 DC and AC Operating Conditions Min. Typ. Max. – 500 May, 2010 Units ...
Page 125
... RESETn Released to TXCLK Valid Figure 9-17. Hardware Reset and Power-Down Timing Diagram REF_IN RESETn TXCLK Valid Power Consumption (AC only) ICS1893BF, Rev. F, 5/13/10 Parameter t1 t2 Copyright © 2009, IDT, Inc. All rights reserved. 125 Chapter 9 DC and AC Operating Conditions Condi- Min. Typ. Max. tions – – 60 – ...
Page 126
... Figure 9-18. 10Base-T Heartbeat (SQE) Timing Diagram TXEN TXCLK COL ICS1893BF, Rev. F, 5/13/10 Chapter 9 DC and AC Operating Conditions Section 6.5.10, “10Base-T Operation: SQE Conditions 10Base-T Half Duplex 10Base-T Half Duplex t1 t2 Copyright © 2009, IDT, Inc. All rights reserved. 126 Min. Typ. Max. Units – 850 1500 ns – ...
Page 127
... Figure 9-19. 10Base-T Jabber Timing Diagram TXEN TP_TX COL ICS1893BF, Rev. F, 5/13/10 Chapter 9 DC and AC Operating Conditions Section 6.5.9, “10Base-T Operation: Conditions 10Base-T Half Duplex 10Base-T Half Duplex t1 Copyright © 2009, IDT, Inc. All rights reserved. 127 Min. Typ. Max. Units 20 – 300 – ...
Page 128
... Figure 9-20. 10Base-T Normal Link Pulse Timing Diagram TP_TXP ICS1893BF, Rev. F, 5/13/10 Figure 9-20 shows the timing diagram for the time periods. Parameter 10Base-T 10Base Copyright © 2009, IDT, Inc. All rights reserved. 128 Chapter 9 DC and AC Operating Conditions Conditions Min. Typ. Max. Units – 100 – ...
Page 129
... Twisted Pair Transmit Signal FLP Burst Differential Twisted Pair Transmit Signal ICS1893BF, Rev. F, 5/13/10 Parameter Conditions Data Pulse Copyright © 2009, IDT, Inc. All rights reserved. 129 Chapter 9 DC and AC Operating Conditions Min. Typ. Max. – – 90 – – – ...
Page 130
... ICS1893BF Data Sheet - Release Chapter 10 Physical Dimensions of ICS1893BF Package Figure 10-1. ICS1893BF 300 mil SSOP Physical Dimensions ICS1893BF, Rev. F, 5/13/10 Chapter 10 Physical Dimensions of ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 130 May, 2010 ...
Page 131
... ICS1893BF Data Sheet Rev Release Figure 10-2. ICS1893BK Thermally Enhanced, Very Thin, Fine Pitch, Quad Flat / No Lead Plastic Package ICS1893BF, Rev. F, 5/13/10 Chapter 10 Physical Dimensions of ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 131 May, 2010 ...
Page 132
... ICS1893BF Data Sheet - Release Chapter 11 Ordering Information Figure 11-1. shows ordering information for the ICS1893BF. Part / Order Number ICS1893BFLF 1893BFLF ICS1893BFLFT 1893BFLF ICS1893BFILF 1893BFILF ICS1893BFILFT 1893BFILF ICS1893BKLF 1893BKLF ICS1893BKLFT 1893BKLF ICS1893BKILF 1893BKILF ICS1893BKILFT 1893BKILF 11.1 Marking Diagram Notes: 1. Line 3: ###### = Lot number. 2. Line 4: YYWW = Date code. ...
Page 133
... ICS1893BF Data Sheet Rev Release Integrated Device Technology, Inc. Web Site: ICS1893BF, Rev. F, 5/13/10 http://www.idt.com Copyright © 2009, IDT, Inc. All rights reserved. 133 Chapter 11 Ordering Information May, 2010 ...