KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet
KSZ8851-16MLLU TR
Specifications of KSZ8851-16MLLU TR
Related parts for KSZ8851-16MLLU TR
KSZ8851-16MLLU TR Summary of contents
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... TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface. The KSZ8851-16MLL is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature-grade version of the KSZ8851-16MLLI and a qualified AEC-Q100 Automotive version of the KSZ8851- 16MLLU are also available (see “ ...
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... Commercial Temperature Range: 0°C to +70°C Industrial Temperature Range: –40°C to +85°C May 2012 Flexible package options available in 48-pin (7mm x 7mm) LQFP KSZ8851-16MLL or 128-pin PQFP KSZ8851-16/32MQL Additional Features In addition to offering all of the features of a Layer 2 controller, the KSZ8851-16MLL offers: ...
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... In 16-bit bus mode, the SD1 bit must set to “1” when CMD = 1 during DMA access. Remove auto-enqueue function, add the reset circuit. Update the description for the register PMECR Bits [1,0]. Add KSZ8851MLLU Automotive part. Add the description for the register TXCR bit 7. Update read/write timing diagram for Asynchronous Cycle. Add power sequence descriptions in the reset timing section ...
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... Address Filtering Function ..........................................................................................................................24 Clock Generator..........................................................................................................................................25 Bus Interface Unit (BIU) ..............................................................................................................................26 Supported Transfers ...................................................................................................................................26 Physical Data Bus Size...............................................................................................................................26 Little and Big Endian Support .....................................................................................................................26 Asynchronous Interface ..............................................................................................................................26 BIU Summation...........................................................................................................................................27 Queue Management Unit (QMU) ................................................................................................................27 Transmit Queue (TXQ) Frame Format........................................................................................................27 Frame Transmitting Path Operation in TXQ ...............................................................................................29 May 2012 4 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Micrel, Inc. Driver Routine for Transmit Packet from Host Processor to KSZ8851-16MLL ...........................................29 Receive Queue (RXQ) Frame Format ........................................................................................................32 Frame Receiving Path Operation in RXQ ...................................................................................................32 Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor ............................................33 EEPROM Interface .....................................................................................................................................34 Loopback Support.......................................................................................................................................35 Near-end (Remote) Loopback ....................................................................................................................35 Far-end (Local) Loopback...........................................................................................................................35 CPU Interface I/O Registers ...............................................................................................................................36 I/O Registers ...
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... Indirect Access Data Low Register (0xD0 – 0xD1): IADLR ........................................................................62 Indirect Access Data High Register (0xD2 – 0xD3): IADHR .......................................................................62 Power Management Event Control Register (0xD4 – 0xD5): PMECR........................................................63 Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR ................................................................64 PHY Reset Register (0xD8 – 0xD9): PHYRR .............................................................................................64 May 2012 6 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Additional MIB Information..........................................................................................................................72 (1) Absolute Maximum Ratings .............................................................................................................................73 (2) Operating Ratings ............................................................................................................................................73 (4, 5) Electrical Characteristics ...............................................................................................................................73 Timing Specifications..........................................................................................................................................75 Asynchronous Read and Write Timing .......................................................................................................75 Auto Negotiation Timing..............................................................................................................................76 Reset Timing...............................................................................................................................................77 EEPROM Timing.........................................................................................................................................78 Selection of Isolation Transformers ....................................................................................................................80 Selection of Reference Crystal ...........................................................................................................................80 Package Information...........................................................................................................................................81 Acronyms and Glossary......................................................................................................................................82 May 2012 7 KSZ8851-16MLL/MLLI 68 M9999-050112-2.1 ...
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... Figure 3. Typical Straight Cable Connection ........................................................................................................................ 20 Figure 4. Typical Crossover Cable Connection .................................................................................................................... 21 Figure 5. Auto Negotiation and Parallel Operation ............................................................................................................... 22 Figure 6. KSZ8851-16MLL 8-Bit and 16-Bit Data Bus Connections..................................................................................... 27 Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram .................................................................................... 30 Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................... 30 Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................... 31 Figure 9 ...
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... Table 7. Transmit Byte Count Format.................................................................................................................................. 28 Table 8. Registers Setting for Transmit Function Block....................................................................................................... 29 Table 9. Frame Format for Receive Queue ......................................................................................................................... 32 Table 10. Registers Setting for Receive Function Block...................................................................................................... 32 Table 11. KSZ8851-16MLL EEPROM Format..................................................................................................................... 34 Table 12. Format of MIB Counters....................................................................................................................................... 71 Table 13. Port 1 MIB Counters Indirect Memory Offsets ..................................................................................................... 72 Table 14. Electrical Characteristics...................................................................................................................................... 74 Table 15 ...
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... Micrel, Inc. Pin Configuration May 2012 Figure 2. 48-Pin LQFP 10 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Power Management Event (default active low asserted (low or high depends on polarity set in PMECR register) when one of the wake-on-LAN events is detected by KSZ8851-16MLL. The KSZ8851-16MLL is requesting the system to wake up from low power mode. Interrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4 ...
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... Shared Data Bus bit 10. Data D10 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode. Shared Data Bus bit 9. Data D9 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode. Digital ground 12 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Shared Data Bus bit 1. Data D1 access when CMD=0. In 8-bit mode, this is address A1 access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1. Shared Data Bus bit 0. Data D0 access when CMD=0. In 8-bit mode, this is address A0 access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1. 13 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... NC or Pull-down (default) = Little Endian This pin value is latched into register CCR, bit 10. When this pin is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to program either Little (bit11=0 default) Endian mode or Big (bit11=1) Endian mode. 14 KSZ8851-16MLL/MLLI Pin Function M9999-050112-2.1 ...
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... The energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8851-16MLL is not connected to an active link partner. For example, if cable is not present connected to a powered down partner, the KSZ8851-16MLL can automatically enter to the low power state in energy detect mode. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851-16MLL can automatically power up to normal power state in energy detect mode ...
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... PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851M can automatically enabled the PHY power up to normal power state from power saving mode. ...
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... If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. If the KSZ8851-16MLL controller detects the data sequence, however, it then alerts the PC’s power management circuitry (assert the PME pin) to wake up the system. ...
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... RXP1 or RXM1 input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8851-16MLL decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. ...
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... The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for the KSZ8851-16MLL device. This feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers ...
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... Straight Cable A straight cable connects an MDI device to an MDI-X device or an MDI-X device to an MDI device. The following diagram shows a typical straight cable connection between a network interface card (NIC) and a switch, or hub (MDI-X). May 2012 Figure 3. Typical Straight Cable Connection 20 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... If auto negotiation is not supported or the link partner to the KSZ8851-16MLL is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...
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... Micrel, Inc. May 2012 Figure 5. Auto Negotiation and Parallel Operation 22 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... If P1SCLMD[14:13]=11, this indicates an invalid test, and occurs when the KSZ8851-16MLL is unable to shut down the link partner. In this instance, the test is not run not possible for the KSZ8851-16MLL to determine if the detected signal is a reflection of the signal generated or a signal from another source. ...
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... If backpressure is required, the KSZ8851-16MLL sends preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8851-16MLL discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state ...
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... Notes: 1. Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set RXCR1 register. 2. The KSZ8851-16MLL will discard frame with SA same as the MAC address if bit[0] is set in RXCR2 register. Clock Generator The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz oscillator (as described in the pin description) ...
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... Shared Data bus SD[15:0] for Address, Data and Byte Enable, Command (CMD), Chip Select Enable (CSN), Read (RDN), Write (WRN) and Interrupt (INTRN). Physical Data Bus Size The BIU supports an 8-bit or 16-bit host standard data bus. Depending on the size of the physical data bus, the KSZ8851- 16MLL can support 8-bit or 16-bit data transfers. For example, For a 16-bit data bus mode, the KSZ8851-16MLL allows an 8-bit and 16-bit data transfer ...
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... CMD=1) then read or write this register data (when CMD=0). If both RDN and WRN signals in the system are only used for KSZ8851-16MLL, the CSN pin can be forced to active low to simplify the system design. The CMD pin can be connected to host address line HA0 for 8-bit bus mode or HA1 for 16-bit bus mode. ...
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... On transmit, all bytes are provided by the CPU, including the source address. The KSZ8851-16MLL does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the KSZ8851-16MLL treated transparently as data both for transmit operations. ...
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... Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to be cleared before setting up another new TX frame. When this bit is written as 1, the KSZ8851-16MLL will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR (0x9E) register ...
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... TXQ write access, then Host starts write transmit data (control word, byte count and pkt data) to TXQ memory. This is moving transmit data from Host to KSZ8851M TXQ memory until whole Write an “0” to RXQCR[3] reg to end Write an “1” to TXQCR[0] reg to issue a transmit command (manual-enqueue) to the TXQ ...
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... TXQ write access, then Host starts write transmit data (control word, byte count and pkt data) to TXQ memory. This is moving transmit data from Host to KSZ8851M TXQ memory until all Write an “0” to RXQCR[3] reg to end Option to read ISR[14] reg, it indicates that the TXQ has completed to transmit all pkts to the PHY port, then Write “ ...
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... RX interrupt in ISR[13] and indicate the status in RXQCR[12]. To program received data byte count value. When the number of received bytes in RXQ exceeds this RXDBCTR[15:0](0x8E) threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851-16MLL will generate RX interrupt in ISR[13] and indicate the status in RXQCR[11]. IER[13](0x90) Set bit 13 to enable receive interrupt in Interrupt Enable Register ...
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... Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor The software driver receives data packet frames from the KSZ8851-16MLL device either as a result of polling or an interrupt based service. When an interrupt is received, the OS invokes the interrupt service routine that is in the interrupt vector table ...
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... KSZ8851 will uPDate next receive frame header status and byte count registers (RXFHSR/RXFHBCR). EEPROM Interface It is optional in the KSZ8851-16MLL to use an external EEPROM. The EED_IO (pin 9) must be pulled high to use external EEPROM otherwise this pin pulled low or floating without EEPROM. An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the host MAC address ...
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... PHY port will be set to 100BASE-TX full-duplex mode. Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at PHY port 1 of the KSZ8851-16MLL. The loopback path starts at the PHY port’s receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXP1/TXM1) ...
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... Micrel, Inc. CPU Interface I/O Registers The KSZ8851-16MLL provides an SRAM-like asynchronous bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for configuring operational settings, reading or writing control, status information, and transferring packets. The KSZ8851- 16MLL can be programmed to interface with either Big-Endian or Little-Endian processor ...
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... EEPROM Control Register [15:8] Memory BIST Info Register [7:0] MBIR 0x1010 Memory BIST Info Register [15:8] Global Reset Register [7:0] GRR 0x0000 Global Reset Register [15:8] Do Not Reserved None Care Wakeup Frame Control Register [7:0] WFCR 0x0000 Wakeup Frame Control Register [15:8] Do Not Reserved Care 37 KSZ8851-16MLL/MLLI Description M9999-050112-2.1 ...
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... Wakeup Frame 2 Byte Mask 1 Register [7:0] WF2BM1 0x0000 Wakeup Frame 2 Byte Mask 1 Register [15:8] Wakeup Frame 2 Byte Mask 2 Register [7:0] WF2BM2 0x0000 Wakeup Frame 2 Byte Mask 2 Register [15:8] Wakeup Frame 2 Byte Mask 3 Register [7:0] WF2BM3 0x0000 Wakeup Frame 2 Byte Mask 3 Register [15:8] Do Not Reserved None Care 38 KSZ8851-16MLL/MLLI Description M9999-050112-2.1 ...
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... TX Frame Data Pointer Register [15:8] RX Frame Data Pointer Register [7:0] RXFDPR 0x0000 RX Frame Data Pointer Register [15:8] Do Not Reserved None Care RX Duration Timer Threshold Register [7:0] RXDTTR 0x0000 RX Duration Timer Threshold Register [15:8] RX Data Byte Count Threshold Register [7:0] RXDBCTR 0x0000 RX Data Byte Count Threshold Register [15:8] 39 KSZ8851-16MLL/MLLI Description M9999-050112-2.1 ...
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... Flow Control Low Watermark Register [15:8] Flow Control High Watermark Register [7:0] FCHWR 0x0300 Flow Control High Watermark Register [15:8] Flow Control Overrun Watermark Register [7:0] FCOWR 0x0040 Flow Control Overrun Watermark Register [15:8] Do Not Reserved None Care Do Not Reserved None Care Do Not Reserved None Care 40 KSZ8851-16MLL/MLLI Description M9999-050112-2.1 ...
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... PHY 1 PHY ID Low Register [15:8] PHY 1 PHY ID High Register [7:0] PHY1IHR 0x0022 PHY 1 PHY ID High Register [15:8] PHY 1 Auto-Negotiation Advertisement Register [7:0] P1ANAR 0x05E1 PHY 1 Auto-Negotiation Advertisement Register [15:8] PHY 1 Auto-Negotiation Link Partner Ability Register [7:0] P1ANLPR 0x0001 PHY 1 Auto-Negotiation Link Partner Ability Register [15:8] 41 KSZ8851-16MLL/MLLI Description M9999-050112-2.1 ...
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... Port 1 PHY Special Control/Status, LinkMD 0x0000 P1SCLMD Port 1 PHY Special Control/Status, LinkMD Port 1 Control Register [7:0] P1CR 0x00FF Port 1 Control Register [15:8] Port 1 Status Register [7:0] P1SR 0x8080 Port 1 Status Register [15:8] Do Not Reserved None Care Do Not Reserved None Care 42 KSZ8851-16MLL/MLLI Description ® [7:0] ® [15:8] M9999-050112-2.1 ...
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... Not in 16-bit bus mode operation 16-bit bus mode operation. Reserved. Shared data bus mode for data and address 0: Data and address bus are seperated. 1: Data and address bus are shared. Reserved. Reserved. 48-Pin Chip Package To indicate chip package is 48-pin. 0: No, 1: Yes. Reserved. 43 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... On-Chip Bus Control Register (0x20 – 0x21): OBCR This register controls the on-chip bus clock speed for the KSZ8851-16MLL. The default of the on-chip bus clock speed is 125MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance ...
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... EEPROM is not used, the software programs the host MAC address EEPROM is used in the design, the chip host MAC address is loaded from the EEPROM immediately after reset. The KSZ8851-16MLL allows the software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software Access bit is set ...
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... Wake up Frame 0 Enable When set, it enables the Wake up frame 0 pattern detection. When reset, the Wake up frame 0 pattern detection is disabled. Description WF0CRC0 Wake up Frame 0 CRC (lower 16 bits) The expected CRC value of a Wake up frame 0 pattern. Description WF0CRC1 Wake up Frame 0 CRC (upper 16 bits). 46 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... The next 16 bytes mask covering bytes Wake-up frame 0 pattern. Description WF0BM3 Wake-up Frame 0 Byte Mask 3. The last 16 bytes mask covering bytes Wake-up frame 0 pattern. Description WF1CRC0 Wake-up frame 1 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 1 pattern. Description WF1CRC1 47 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... The next 16 bytes mask covering bytes Wake-up frame 1 pattern. Description WF1BM3 Wake-up frame 1 Byte Mask 3. The last 16 bytes mask covering bytes Wake-up frame 1 pattern. Description WF2CRC0 Wake-up frame 2 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 2 pattern. Description 48 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Wake-up frame 2 Byte Mask 3. The last 16 bytes mask covering bytes Wake-up frame 2 pattern. Description WF3CRC0 Wake-up frame 3 CRC (lower 16 bits). The expected CRC value of a Wake up frame 3 pattern. Description WF3CRC1 Wake-up frame 3 CRC (upper 16 bits). The expected CRC value of a Wake up frame 49 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Description Reserved. TCGICMP Transmit Checksum Generation for ICMP When this bit is set, The KSZ8851-16MLL is enabled to transmit ICMP frame (only for non-fragment frame) checksum generation. TCGUDP Transmit Checksum Generation for UDP When this bit is set, The KSZ8851-16MLL is enabled to transmit UDP frame checksum generation ...
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... RXUDPFCC Receive UDP Frame Checksum Check Enable When this bit is set, the KSZ8851 will check for correct UDP checksum for incoming UDP frames. Any received UDP frames with incorrect checksum will be discarded. RXTCPFCC Receive TCP Frame Checksum Check Enable When this bit is set, the KSZ8851 will check for correct TCP checksum for incoming TCP frames ...
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... May 2012 Description RXIPFCC Receive IP Frame Checksum Check Enable When this bit is set, the KSZ8851 will check for correct IP header checksum for incoming IP frames. Any received IP frames with incorrect checksum will be discarded. RXPAFMA Receive Physical Address Filtering with MAC Address Enable ...
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... Description Reserved. IUFFP IPV4/IPV6/UDP Fragment Frame Pass When this bit is set, the KSZ8851-16MLL will pass the checksum check at receive side for IPv4/IPv6 UDP frame with fragment extension header. When this bit is cleared, the KSZ8851-16MLL will perform checksum operation based on configuration and doesn’t care whether it’s a fragment frame or not. ...
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... RXTCPFCS Receive TCP Frame Checksum Status When this bit is set, the KSZ8851 received TCP frame checksum field is incorrect. RXUDPFCS Receive UDP Frame Checksum Status When this bit is set, the KSZ8851 received UDP frame checksum field is incorrect. Reserved RXBF Receive Broadcast Frame When this bit is set, it indicates that this frame has a broadcast address ...
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... RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E, RXDBCT). RXFCTE RX Frame Count Threshold Enable When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) when the number of received frames in RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C, RXFCT). ...
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... SDA Start DMA Access When this bit is written as 1, the KSZ8851-16MLL allows a DMA operation from the host CPU to access either read RXQ frame buffer or write TXQ frame buffer with CSN and RDN or WRN signals while the CMD pin is low ...
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... To program received frame duration timer threshold value in 1us interval. The maximum value is 0xCFFF. When bit 7 set RXQCR register, the KSZ8851-16MLL will set RX interrupt (bit 13 in ISR) after the time starts at first received frame in RXQ buffer and exceeds the threshold set in this register. ...
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... This edge-triggered interrupt status is cleared by writing 1 to this bit. RXIS Receive Interrupt Status When this bit is set, it indicates that the QMU RXQ has received at least a frame from the MAC interface and the frame is ready for the host CPU to process. 58 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... RX frame count register. RXFCT Receive Frame Count Threshold To program received frame count threshold value. When bit 5 set RXQCR register, the KSZ8851-16MLL will set RX interrupt (bit 13 in ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this register. ...
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... The host CPU is used to program the total amount of TXQ buffer space which is required for next total transmit frames size in double-word count. When bit 1 (TXQ memory available monitor) is set TXQCR register, the KSZ8851- 16MLL will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is available based upon the total amount of TXQ space requested by CPU at this register ...
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... FCLWC Flow Control Overrun Watermark Configuration These bits are used to define the QMU RX queue overrun watermark configuration double words count and default is 256 Bytes available buffer space out of 12 Kbyte. Description Family ID Chip family ID Chip ID 0x7 is assigned to KSZ8851-16MLL Revision ID Reserved 61 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Read cycle is enabled (MIB counter will clear after read operation. Table Select 00 = reserved reserved reserved MIB counter selected. Reserved. Indirect Address Bit 4-0 of indirect address for 32 MIB counter locations. Description Indirect Low Word Data Bit 15-0 of indirect data. Description Indirect High Word Data Bit 31-16 of indirect data. 62 KSZ8851-16MLL/MLLI 1 ACT LINK M9999-050112-2.1 ...
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... Micrel, Inc. Power Management Event Control Register (0xD4 – 0xD5): PMECR This register is used to control the KSZ8851-16MLL power management event, capabilities and status. Default Bit R/W Value 11-8 0x0 5-2 0x0 (W1C) May 2012 Description Reserved ...
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... RW May 2012 Description Power Management Mode These two bits are used to control the KSZ8851-16MLL power management mode as below: 00: Normal Operation Mode. 01: Energy Detect Mode. (two states in this mode either low power or normal power) 10: Soft Power Down Mode. 11: Power Saving Mode. ...
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... Half Capable 1 = 10BASE-T half-duplex capable not 10BASE-T half-duplex capable. Reserved. Preamble suppressed Not supported. 65 KSZ8851-16MLL/MLLI Bit is same as: Bit 13 in P1CR Bit 5 in P1CR Bit 15 in P1SR Bit 9 in P1CR Bit 10 in P1CR Bit 14 in P1CR Bit 15 in P1CR Bit is same as: M9999-050112-2 ...
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... Adv 100 Half 1= advertise 100 half-duplex capability not advertise 100 half-duplex capability. Adv 10 Full 1 = advertise 10 full-duplex capability. 66 KSZ8851-16MLL/MLLI Bit is same as: Bit 6 in P1SR Bit 5 in P1SR Bit is same as: Bit 4 in P1CR Bit 3 in P1CR ...
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... Micrel, Inc 4-0 0x01 RO May 2012 not advertise 10 full-duplex capability. Adv 10 Half 1 = advertise 10 half-duplex capability not advertise 10 half-duplex capability. Selector Field 802.3 67 KSZ8851-16MLL/MLLI Bit 0 in P1CR M9999-050112-2.1 ...
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... Force_lnk Force link force link pass normal operation. Reserved. 68 KSZ8851-16MLL/MLLI Bit is same as: Bit 4 in P1SR Bit 3 in P1SR Bit 2 in P1SR Bit 1 in P1SR Bit 0 in P1SR Bit is same as: ...
Page 69
... Advertised flow control capability 1 = advertise flow control (pause) capability suppress flow control (pause) capability from transmission to link partner. Advertised 100BT full-duplex capability 69 KSZ8851-16MLL/MLLI Bit is same as: Bit 0 in P1MBCR Bit 1 in P1MBCR Bit 9 in P1MBCR Bit 3 in P1MBCR Bit 4 in P1MBCR ...
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... Partner 100BT full-duplex capability 1 = link partner 100BT full-duplex capable link partner not 100BT full-duplex capable. Partner 100BT half-duplex capability 1 = link partner 100BT half-duplex capable. 70 KSZ8851-16MLL/MLLI Bit is same as: Bit 7 in P1ANAR Bit 6 in P1ANAR Bit 5 in P1ANAR Bit is same as: Bit 5 in P1MBCR ...
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... R 0xFA – 0xFF: Reserved MIB (Management Information Base) Counters The KSZ8851-16MLL provides 32 MIB counters to monitor the port activity for network management. The MIB counters are formatted as shown below: Bit Name R/W Counter 31-0 RO values Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F. ...
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... Tx total collision, half duplex only A count of frames for which Tx fails due to excessive collisions Successfully Tx frames on a port for which Tx is inhibited by exactly one collision Successfully Tx frames on a port for which Tx is inhibited by more than one collision Table 13. Port 1 MIB Counters Indirect Memory Offsets 72 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Ethernet cable disconnected & Auto-Neg Set Bit [1: PMECR register At low power state V = GND ~ VDD_IO -8mA 8mA OL / is under air velocity 0m/ KSZ8851-16MLL/MLLI (2) VDD_A3.3 .......................................... +3.1V to +3.5V VDD_IO (3.3V) ................................... +3.1V to +3.5V VDD_IO (2.5V) ............................... +2.35V to +2.65V VDD_IO (1.8V) ................................... +1.7V to +1. (3) Junction-to-Ambient ( ) ..........................83.56°C/W JA Junction-to-Case ( ) ...............................35.90°C/W JC Min Typ ...
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... Peak-to-peak 5MHz square wave 100 termination on the differential output 100 termination on the differential output (Peak-to-peak) Table 14. Electrical Characteristics 74 KSZ8851-16MLL/MLLI Min Typ Max Units ±0.95 ±1. ...
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... RDN active to read data valid (bit12=1 in RXFDPR) t6 RDN Read active time (low) WRN Write active time (low) t7 RDN Read inactive time (high) WRN Write inactive time (high) May 2012 Figure 11. Asynchronous Cycle Parameter Table 15. Asynchronous Cycle Timing Parameters 75 KSZ8851-16MLL/MLLI Min Typ Max Unit ...
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... Figure 12. Auto Negotiation Timing Description FLP burst to FLP burst FLP burst width Clock/Data pulse width Clock pulse to data pulse Clock pulse to clock pulse Number of Clock/Data pulses per burst Table 16. Auto Negotiation Timing Parameters 76 KSZ8851-16MLL/MLLI Min Typ Max Unit ...
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... As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement when the KSZ8851-16MLL use a single 3.3V power supply with internal 1.8V LDO also requirement the power-sequencing to power up the 1.8V voltage earlier than VDDIO voltage if the internal 1.8V LDO is not used. At least, the both 1 ...
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... Micrel, Inc. EEPROM Timing Timing Parameter Description tcyc Clock cycle ts Setup time th Hold time May 2012 Figure 14. EEPROM Read Cycle Timing Diagram Min Table 18. EEPROM Timing Parameters 78 KSZ8851-16MLL/MLLI Typ 0.8 (OBCR[1:0]=00 on-chip bus speed @ 125MHz M9999-050112-2.1 Max Unit ...
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... At power-on-reset and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up. May 2012 VCC D1: 1N4148 D1 KSZ8851 RST C 10µF Figure 15. Recommended Reset Circuit VCC R D1 10k RST D2 C 10µF D1, D2: 1N4148 79 KSZ8851-16MLL/MLLI R 10k CPU/FPGA RST_OUT_n M9999-050112-2.1 ...
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... Table 19. Transformer Selection Criteria Part Number H1102 H1260 HB726 S558-5999-U7 LF8505 LF-H41S TLA-6T718 Table 20. Qualified Single Port Magnetics Table 21. Typical Reference Crystal Characteristics 80 KSZ8851-16MLL/MLLI Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Auto MDI-X Number of Port Yes 1 Yes 1 Yes ...
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... Micrel, Inc. Package Information May 2012 Figure 17. 48-Pin (7mm x 7mm) LQFP 81 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' 82 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...
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... A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. Micrel for any damages resulting from such use or sale. © 2008 Micrel, Incorporated. 83 KSZ8851-16MLL/MLLI M9999-050112-2.1 ...