S34ML02G100BHI000 Spansion, S34ML02G100BHI000 Datasheet

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S34ML02G100BHI000

Manufacturer Part Number
S34ML02G100BHI000
Description
Flash 2Gb 3V 25ns NAND Flash
Manufacturer
Spansion
Datasheet

Specifications of S34ML02G100BHI000

Rohs
yes
Memory Type
NAND Flash
Memory Size
2 Gbit
Timing Type
Asynchronous
Access Time
20 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
BGA-63

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Spansion
Embedded
1 Gb, 2 Gb, 4 Gb Densities:
1-bit ECC, x8 and x16 I/O, 3V V
S34ML01G1, S34ML02G1, S34ML04G1
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Publication Number S34ML01G1_04G1
®
SLC NAND Flash Memory for
CC
Notice On Data Sheet Designations
Revision 15
Issue Date March 7, 2013
for definitions.
Spansion
®
SLC NAND Flash Memory for Embedded Cover Sheet

Related parts for S34ML02G100BHI000

S34ML02G100BHI000 Summary of contents

Page 1

... Gb Densities: 1-bit ECC, x8 and x16 I/ S34ML01G1, S34ML02G1, S34ML04G1 Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S34ML01G1_04G1 ...

Page 2

... The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “ ...

Page 3

... Publication Number S34ML01G1_04G1 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com- binations offered may occur ...

Page 4

... Data Protection and Power On / Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2 Ready/Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 Write Protect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6 Pin Capacitance Spansion ® SLC NAND Flash Memory for Embedded S34ML01G1_04G1_15 March 7, 2013 ...

Page 5

... Thin Small Outline Package (TSOP1 .65 7.1.2 63-Pin Ball Grid Array (BGA .66 8. System Interface Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.1 System Bad Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.2 Bad Block Management 10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 March 7, 2013 S34ML01G1_04G1_15 ® Spansion SLC NAND Flash Memory for Embedded 5 ...

Page 6

... Erase Enabling / Disabling Through WP# Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 7.1 TS/TSR 48 — 48-lead Plastic Thin Small Outline mm, Package Outline . . . . . . . . 65 Figure 7.2 VBM063 — 63-Pin BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6 Spansion ® SLC NAND Flash Memory for Embedded S34ML01G1_04G1_15 March 7, 2013 ...

Page 7

... Figure 8.1 Program Operation with CE# Don't Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 8.2 Read Operation with CE# Don't Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 8.3 Page Programming Within a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 9.1 Bad Block Replacement Figure 9.2 Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 March 7, 2013 S34ML01G1_04G1_15 ® Spansion SLC NAND Flash Memory for Embedded 7 ...

Page 8

... Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 5.3 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 5.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 5.5 DC Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 5.6 Pin Capacitance (TA = 25°C, f=1.0 MHz Table 5.7 Program / Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 9.1 Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8 Spansion ® SLC NAND Flash Memory for Embedded S34ML01G1_04G1_15 March 7, 2013 ...

Page 9

... General Description The Spansion S34ML01G1, S34ML02G1, and S34ML04G1 series is offered in 3.3 V supply, and with x8 or x16 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently possible to preserve valid data while old data is erased. The page size for x8 is (2048 + 64 spare) bytes ...

Page 10

... Serial number (unique identifier), which allows the devices to be uniquely identified.  Read ID2 extension. These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the data sheet. For more details about them, contact your nearest Spansion sales office. Device S34ML01G1 ...

Page 11

... VCC ( I/ I/ I/O2 I/ ® Spansion SLC NAND Flash Memory for Embedded x8 x16 48 (1) VSS VSS NC I/O15 NC I/O14 NC I/O13 I/O7 I/O7 I/O6 I/O6 I/O5 I/O5 I/O4 I/O4 NC I/O12 (1) VCC VCC VCC VCC 36 VSS VSS NC NC (1) VCC ...

Page 12

... The PCB track widths must be sufficient to carry the currents required during program and erase operations internal voltage detector disables all functions whenever V program/erase during power transitions. 12 Spansion Figure 1.4 63-VFBGA Contact, x16 Device (Balls Down, Top View) ...

Page 13

... HV Generation 2048 Mbit + 64 Mbit (2 Gb Device) 4096 Mbit + 128 Mbit (4 Gb Device) NAND Flash Memory Array Command Interface Logic Command Register Data Register I/O0~I/O7 (x8) I/O0~I/O15 (x16) ® Spansion SLC NAND Flash Memory for Embedded PAGE Buffer Y Decoder I/O Buffer 13 ...

Page 14

... Array Organization 1024 Blocks per Plane Page Buffer 1024 Blocks per Plane Page Buffer 14 Spansion Figure 1.6 Array Organization — x8 Plane( 1022 1023 I/O [7:0] 2048 bytes 64 bytes Array Organization (x8) Figure 1.7 Array Organization — x16 Plane( 1022 1023 ...

Page 15

... A2 (CA2) A3 (CA3) A8 (CA8) A9 (CA9) A10 (CA10) A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A19 (BA2) A20 (BA3) A21 (BA4) A22 (BA5) ® Spansion SLC NAND Flash Memory for Embedded I/O3 I/O4 I/O5 I/O6 A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7) Low Low Low A16 (PA4) A17 (PA5) ...

Page 16

... A0 - A10: column address in the page  A11 - A16: page address in the block  A17: plane address (for multiplane operations) / block address (for normal operations)  A18 - A27: block address 16 Spansion Table 1.4 Address Cycle Map — Device (6) ...

Page 17

... Low A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A19 (BA1) A20 (BA2) A21 (BA3) A22 (BA4) A27 (BA9) A28 (BA10) Low Low ® Spansion SLC NAND Flash Memory for Embedded I/O4 I/O5 I/O6 I/O7 A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7) Low Low Low Low A16 (PA4) ...

Page 18

... Write Enable. Moreover, for commands that start a modify operation (program/ erase) the Write Protect pin must be high. See the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus configuration (x8 or x16). Refer to Table 1.3 18 Spansion Table 1.6 Mode Selection CLE ALE ...

Page 19

... In Standby, the device is deselected, outputs are disabled, and power consumption is reduced. March 7, 2013 S34ML01G1_04G1_15 Figure 6.3 on page 44 and Table 5.4 on page 41 to Figure 6.23 and Table 5.4 on page 41 ® Spansion SLC NAND Flash Memory for Embedded for details of the timing for details of the timings 19 ...

Page 20

... ONFI Multiplane Cache Program (Start/Continue) Multiplane Cache Program (End) ONFI Multiplane Cache Program (End) Read ID Read ID2 Read ONFI Signature Read Parameter Page One-time Programmable (OTP) Area Entry 20 Spansion Table 3.1 Command Set 1st Cycle 2nd Cycle 3rd Cycle 00h 30h ...

Page 21

... R/B pin. Once the R and Figure 6.12 on page 49 as references. Figure 6.9 on page 47 Table 5.7 on page 43. In addition, pages must be sequentially programmed ® Spansion SLC NAND Flash Memory for Embedded ). The system R and Figure 6.11 on page 48 detail the Section 3.8 on page 26 for ...

Page 22

... Spansion describes the sequences using the legacy protocol. In this case, the block address describes the sequences using the ONFI protocol ...

Page 23

... Din tADL Page N ADDR ADDR ADDR Din Din tADL Page M ® Spansion SLC NAND Flash Memory for Embedded Din Din Din CMD . . . Dn D1 10h tWB tPROG CMD ADDR ADDR R1 R2 10h tWB tPROG Page M Figure 3.2. ...

Page 24

... If a Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted block is erased under continuous power conditions before that block can be trusted for further programming and reading operations. 24 Spansion details the sequence. ...

Page 25

... for performance information. 52), or Copy Back Program command (85h) with the address cycles of destination page 52. As noted in Section 1. on page 9 ® Spansion SLC NAND Flash Memory for Embedded Figure 6.16 on page 51 Figure 6.17 on page 51 describes the ). In case of DBSY Section 3.9 on page 28 ...

Page 26

... Data Input” given EDC unit can be executed several times during one page program sequence, but data cannot be written to any column address more than once before the program is initiated. 26 Spansion Figure 6.21 on page 54 26) is triggered with confirm command ‘36h’ instead ‘35h’, Copy Back Read from target ) voltage ...

Page 27

... Spansion SLC NAND Flash Memory for Embedded Table 3.2 for specific EDC Coding Pass: 0; Fail error: 0; Error: 1 Invalid: 0; Valid: 1 — — Busy: 0; Ready: 1 Busy: 0; Ready: 1 Protected: 0 ...

Page 28

... Status Register definitions. The command register remains in Status Read mode until further commands are issued. The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it. 28 Spansion Table 3.4 Page Organization in EDC Units by Address Main Field (Column 0-2047) ...

Page 29

... Write Protect Write Protect Figure 6.26 on page 56 for further details. The Status Register can also 57), device goes busy for a short time (t Figure 6.29 on page 57), device goes busy for a short time (t ® Spansion SLC NAND Flash Memory for Embedded Cache Program / Coding Cache Reprogram N Page ...

Page 30

... The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while programming page N. The status bit is valid upon I/O5 status bit changing to 1. I/O1 may be read together with I/O0. 30 Spansion ® SLC NAND Flash Memory for Embedded ...

Page 31

... DBSY CBSYW shows the ONFI protocol for the multiplane cache program operation. For both for more details. Section 3.9 on page 28 ® Spansion SLC NAND Flash Memory for Embedded and Figure 6.31 on page 58 for more ). After all data from the cache registers Figure 6.32 for further information. ...

Page 32

... Figure 6.34 on page 61 meaning. Density Device Identifier Byte 1st 2nd 3rd 4th 5th (S34ML02G1, S34ML04G1) 32 Spansion shows the operation sequence, while Table 3.6 Read ID for Supported Configurations Org V 1st CC 01h x8 01h 01h 3.3V 01h x16 ...

Page 33

... Description I/O7 I/ 128 kB 256 kB 512 Reserved 1 Reserved x16 1 ® Spansion SLC NAND Flash Memory for Embedded I/O5 I/O4 I/O3 I/O2 I/O1 I/ I/O5 I/O4 I/O3 I/O2 I/O1 I/ ...

Page 34

... The address for S34ML02G1 and S34ML04G1 will be 00h-02h-02h-00h-00h. The ID2 data can then be read from the device by pulsing RE#. The command register remains in Read ID2 mode until further commands are issued to it. ID2 values are all 0xFs, unless specific values are requested when ordering from Spansion. 3.18 Read ONFI Signature To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i ...

Page 35

... Read Cache commands supports Page Cache Program command Manufacturer Information Block Memory Organization Block ® Spansion SLC NAND Flash Memory for Embedded shows the operation sequence, Values 4Fh, 4Eh, 46h, 49h 02h, 00h S34ML01G100 (x8): 14h, 00h S34ML02G100 (x8): 1Ch, 00h ...

Page 36

... 139-140 M t CCS 141-163 Reserved (0) 164-165 M Vendor specific Revision number 36 Spansion Table 3.12 Parameter Page Description (Sheet Description 4-7 Column address cycles 0-3 Row address cycles 5-7 Reserved partial page layout is partial page data followed by partial page spare ...

Page 37

... Figure 6.39 on page and V on the other hand) are shorted together at all times. SSQ Figure 6.39 on page 63. The two-step command sequence for ® Spansion SLC NAND Flash Memory for Embedded Values 00h S34ML01G100 (x8): E9h, 0Ah S34ML02G100 (x8): 3Bh, C5h S34ML04G100 (x8): 45h, 8Eh S34ML01G104 (x16): 9Bh, 7Ch ...

Page 38

... R/B# outputs to be Or-tied. Because pull-up resistor value is related appropriate value can be obtained with the reference chart shown in For example, for a particular system with output load, t whereas for a particular load of 50 pF, Spansion measured shown in Vcc GND Rp value guidence Rp (min. 3.3V part) = ...

Page 39

... (similarly to Figure 6.26 on page 56). At the end of this time, the command RST Table 3.5 on page 29 Figure 6.40 and Figure 6.41 on page WE# I/O[7:0] Valid WP# > 100 ns ® Spansion SLC NAND Flash Memory for Embedded for more information on device status. ns prior to raising the WE# pin WW 64. Sequence Aborted 39 ...

Page 40

... Maximum Voltage may overshoot to VCC+2.0V during transition and for less than 20 ns during transitions. 5.3 AC Test Conditions Parameter Input Pulse Levels Input Rise And Fall Times Input And Output Timing Levels Output Load (2.7V - 3.6V) 40 Spansion Table 5.1 Valid Blocks Symbol Min N 1004 VB ...

Page 41

... RR t RST WHR depends partly on t (CE# low to RE# low CEA CR REA ® Spansion SLC NAND Flash Memory for Embedded Min Max 10 — 5 — 10 — 70 — 10 — 5 — — — 10 — 10 — — — ...

Page 42

... Pin Capacitance Parameter Input Input / Output Note: 1. For the stacked devices version the Input [number of stacked chips] and the Input/Output [number of stacked chips]. 42 Spansion Table 5.5 DC Characteristics and Operating Conditions Symbol Test Conditions Power-Up Current ...

Page 43

... Copy Back Program may not meet this specification when copying from an odd PROG Figure 6.1 Command Latch Cycle tCLS tCLH tCS tCH tWP tALS tALH tDS tDH Command ® Spansion SLC NAND Flash Memory for Embedded Description Min Typ Max Unit t — 200 700 µs PROG t — ...

Page 44

... Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. CLE CE# ALE WE# I/Ox 44 Spansion Figure 6.2 Address Latch Cycle tCLS tCS tWC tWC tWP ...

Page 45

... tRR Figure 6.5 Data Output Cycle Timing (EDO) tRC tRP tREH tREA tREA tRLOH Dout ® Spansion SLC NAND Flash Memory for Embedded tCHZ tREA tCOH tRHZ tRHOH tCHZ tCOH tRHZ tRHOH Dout 45 ...

Page 46

... If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page buffer. 6.7 Page Read Operation (Intercepted by CE#) CLE CE# WE# ALE RE# 00h I/Ox R/B# 46 Spansion Figure 6.6 Page Read Operation (Read One Page) tWB Row Col. Col. Row Row 30h Add. 1 Add. 2 Add ...

Page 47

... Row. Row. Row. Din Din N M Add2 Add3 Add1 Add1 Add2 byte Row Address Serial Input ® Spansion SLC NAND Flash Memory for Embedded CE# don’t care Dout Dout Dout Dout Dout Dout Dout Don’ ...

Page 48

... WE# rising edge of final address cycle to the WE# rising edge of first data cycle. ADL 2. For EDC operation only one time Random Data Input is possible at same address. 48 Spansion Figure 6.10 Page Program Operation Timing with CE# Don’t Care Col ...

Page 49

... A0 ~ A11: Valid A0 ~ A11: Valid A12 ~ A17: Fixed ‘Low’ A12 ~ A17: Valid A18: Fixed ‘Low’ A19 ~ A28: Fixed ‘Low’ A19 ~ A28: Valid ® Spansion SLC NAND Flash Memory for Embedded tCLR tWHR tREA Dout Col. Dout Col. ...

Page 50

... The block address bits must be the same except for the bit(s) that select the plane. 6.14 Block Erase Operation CLE CE# tWC WE# ALE RE# 60h I/Ox R/B# Auto Block Erase Setup Command 50 Spansion Figure 6.14 Multiplane Page Program (ONFI 1.0 Protocol) ADDR ADDR ADDR tADL ...

Page 51

... A19 ~ A28 : Valid Figure 6.17 Multiplane Block Erase (ONFI 1.0 Protocol) R3 D1h 60h IEBSY ® Spansion SLC NAND Flash Memory for Embedded tWHR tWB tBERS h 0 I/O0 70h Busy Read Status Command I Successful Erase I Error in plane D0h ...

Page 52

... Copy Back Program Operation With Random Data Input — S34ML02G1 and S34ML04G1 00h I/O Read Code R/B# I/O 00h Read Code R/B# 52 Spansion Figure 6.18 Copy Back Read with Optional Data Readout Source 35h Data Outputs 85h Copy Back Code tR (Read Busy time) Busy Figure 6 ...

Page 53

... Plane 0 Plane 1 Source Page Source Page Target Page Target Page (2) (3) (3) Spare Field Data Field ® Spansion SLC NAND Flash Memory for Embedded tR 35h tPROG Add. (5 cycles) 10h 70h Destination Address A0 ~ A11 : Fixed ‘Low’ A12 ~ A17 : Valid A18 : Fixed ‘High’ ...

Page 54

... R1B-R3B Row address for page B. R1B is the least significant byte. 5. The block address bits must be the same except for the bit(s) that select the plane. 6.19 Read Status Cycle Timing CLE CE# WE# RE# I/Ox 54 Spansion Figure 6.21 Multiplane Copy Back Program (ONFI 1.0 Protocol 11h A ...

Page 55

... CLE WE# ALE RE# I/O0-7 78h March 7, 2013 S34ML01G1_04G1_15 Figure 6.23 Read Status Enhanced Cycle Figure 6.24 Read Status Timing tWHR SR tREA Figure 6.25 Read Status Enhanced Timing tWHR tAR ® Spansion SLC NAND Flash Memory for Embedded 55 ...

Page 56

... A CE# CLE ALE WE# tWB RE# I/Ox Dout 31h R/B# Data Cache 1 Page Buffer Cell Array Page N 56 Spansion Figure 6.26 Reset Operation Timing t RST Figure 6.27 Read Cache Operation Timing tWB tWB tRR Col. Row Row Row 30h 31h Add 2 Add 1 Add 2 ...

Page 57

... R2 R3 31h tWB tCBSYR Figure 6.30 Read Cache Timing, End Of Cache Operation Dout Dout Dout CMD 3Fh tRR tWB tCBSYR ® Spansion SLC NAND Flash Memory for Embedded Dout Dout CMD Dout ... Dn 31h D0 tWB tRR tCBSYR ADDR CMD Dout Dout Dout ...

Page 58

... Cache Program CLE CE# tWC WE# ALE RE# Col. 80h I/Ox Add1 Column Address R/B# CLE CE# WE# ALE RE# I/Ox 80h R/ Spansion Figure 6.31 Cache Program tWB Col. Row. Row. Row. Din Din 15h 80h N M Add2 Add1 Add2 Add3 Row Address tCBSYW tWC tADL Col ...

Page 59

... Din Din 81h 11h Add2 Add1 Add2 Add3 N M Row Address tDBSY ® Spansion SLC NAND Flash Memory for Embedded Address Input Data Input 15h A13~A17: Valid A18: Fixed ‘High’ A19~A31: Valid t CBSYW Address Input Data Input 10h A13~A17: Valid A18: Fixed ‘ ...

Page 60

... Notes: 1. The block address bits must be the same except for the bit(s) that select the plane. 2. Read Status register (70h) is used in the figure. Read Status Enhanced (78h) can be also used. 60 Spansion Figure 6.33 Multiplane Cache Program (ONFI 1.0 Protocol) ...

Page 61

... Figure 6.35 Read ID2 Operation Timing tR ID2 Data ID2 Data 4 Cycle Address Read ID2 1st Cycle 2nd Cycle Confirm Command (Note 1) Busy ® Spansion SLC NAND Flash Memory for Embedded F1h 00h 1Dh DAh 90h 95h 44h DCh 90h 95h 54h Device ...

Page 62

... CLE WE# ALE RE# IO0~7 90h 6.29 Read Parameter Page Timing CLE WE# ALE RE# IO0-7 ECh R/B# 62 Spansion Figure 6.36 ONFI Signature Timing t WHR 20h 4Fh tREA Figure 6.37 Read Parameter Page Timing 00h t R ® SLC NAND Flash Memory for Embedded 4Eh 46h 49h ...

Page 63

... Volt for 3.0V supply devices. TH March 7, 2013 S34ML01G1_04G1_15 Figure 6.38 OTP Entry Timing 04h 19h Figure 6.39 Power On and Data Protection Timing max Operation ® Spansion SLC NAND Flash Memory for Embedded Vcc(min) Vth don’t care V IL don’t care 63 ...

Page 64

... WP# Handling WE I/Ox 80h WP# R/B# WE I/Ox 60h WP# R/B# 64 Spansion Figure 6.40 Program Enabling / Disabling Through WP# Handling WE# 10h I/Ox WP# R/B# Figure 6.41 Erase Enabling / Disabling Through WP# Handling WE# D0h I/Ox WP# R/B# ® SLC NAND Flash Memory for Embedded t WW 80h 10h t WW 60h D0h S34ML01G1_04G1_15 March 7, 2013 ...

Page 65

... AND 0.25mm (0.0098") FROM THE LEAD TIP. 0.50 BASIC 8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM 0.60 0.70 THE SEATING PLANE. --- 8 9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. --- 0.20 48 ® Spansion SLC NAND Flash Memory for Embedded -C- . THE SEATING PLANE IS 3664 \ f16-038.10 \ 11.6.7 65 ...

Page 66

... Øb 0. A3-A8,B2-B8,C1,C2,C9,C10 D1,D2,D9,D10,E1,E2,E9,E10 F1,F2,F9,F10,G1,G2,G9,G10 H1,H2,H9,H10,J1,J2,J9,J10 K1,K2,K9,K10,L3-L8,M3-M8 66 Spansion Figure 7.2 VBM063 — 63-Pin BGA Package VBM 063 M0-207(M) NOTE PACKAGE NOM MAX --- 1.00 PROFILE --- --- BALL HEIGHT 11.00 BSC BODY SIZE 9.00 BSC BODY SIZE 8 ...

Page 67

... Figure 8.2 Read Operation with CE# Don't Care If sequential row read enabled, CE must be held low during tR Cycle ® Spansion SLC NAND Flash Memory for Embedded CE# don’t care Data Input CE# don’t care ...

Page 68

... Page 63 Page 31 Page 2 Page 1 Page 0 From the LSB page to MSB page 68 Spansion Figure 8.3 Page Programming Within a Block (64) (32) (3) (2) (1) Data Register DATA IN : Data (1) Data (64) ® SLC NAND Flash Memory for Embedded Page 63 (64) (1) Page 31 (3) Page 2 (32) ...

Page 69

... Table 9.1 Block Failure Operation Erase Program Read Figure 9.1 Bad Block Replacement Block A (2) Data (1) Failure (3) FFh buffer memory of the controller ® Spansion SLC NAND Flash Memory for Embedded Recommended Procedure Block Replacement Block Replacement ECC (1 bit / 512+16 byte) Block B Data th N page FFh 69 ...

Page 70

... Note: 1. Check for FFh at the 1st byte in the spare area of the 1st, 2nd, and last pages. 70 Spansion 9.2. The host is responsible to detect and track bad blocks, both factory bad blocks Figure 9 ...

Page 71

... NAND, single die Technology 1 = Spansion NAND Revision 1 (4x nm) Density 01G = 1 Gb 02G = 2 Gb 04G = 4 Gb Device Family S34ML - 3V Spansion SLC NAND Flash Memory for Embedded Valid Combinations Bus Package Temperature Technology Width Type Range 1 00 ® Spansion SLC NAND Flash Memory for Embedded ...

Page 72

... Revision History Section Revision 01 (April 16, 2012) Initial release Revision 02 (May 4, 2012) Global Removed Spansion Confidential designation Read Status Enhanced Updated text Command Set Updated table: Command Set Read ID Updated table: Read ID for Supported Configurations Legacy Read ID Removed section heading: Legacy Read ID ...

Page 73

... Added text S34ML04G1 Block Erase Added text March 7, 2013 S34ML01G1_04G1_15 Description corrected Output low voltage Test Conditions corrected Output low current (R/B#) Typ and Max values Min and T Min ALS DS ® Spansion SLC NAND Flash Memory for Embedded 73 ...

Page 74

... Page Read Operation Page Read Operation (Read One Page) figure: added note Read ID2 Operation Timing figure: Read ID2 Operation Timing 74 Spansion Description corrected Electrical Parameters Block values for bytes 129-130 and bytes 131-132 corrected Vendor Block values for bytes 254-255 ...

Page 75

... Status / EDC Read Cycle figure: removed Note Revision 15 (March 7, 2013) Updated section Ready/Busy Corrected Ready/Busy Pin Electrical Application figure March 7, 2013 S34ML01G1_04G1_15 Description CLS ® Spansion SLC NAND Flash Memory for Embedded and Max value for t CEA 75 ...

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... Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure ...

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