MAX3107EVKIT+ Maxim Integrated, MAX3107EVKIT+ Datasheet
MAX3107EVKIT+
Specifications of MAX3107EVKIT+
Related parts for MAX3107EVKIT+
MAX3107EVKIT+ Summary of contents
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... HVAC or Building Control Pin Configurations appear at end of data sheet. Functional Diagrams continued at end of data sheet. SPI is a trademark of Motorola, Inc. UCSP is a trademark of Maxim Integrated Products, Inc. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com UART with 128-Word FIFOs 24-Pin, Lead-Free TQFN (3 ...
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... Auto Transceiver Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Auto Hardware Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AutoRTS Control AutoCTS Control Auto Software (XON/XOFF) Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Transmitter Flow Control Receiver Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FIFO Interrupt Triggering Low-Power Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Forced Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Autosleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 TABLE OF CONTENTS Maxim Integrated ...
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... Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Applications Information Startup and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Interrupts and Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Logic-Level Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Connector Pin Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 RS-232 5x3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Package Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Maxim Integrated 2 C UART with 128-Word FIFOs TABLE OF CONTENTS (continued) MAX3107 3 ...
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... Figure 25. Connector Sharing with a USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 26. RS-232 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 27. RS-485 Half-Duplex Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 1. StopBits Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 2. Length[1:0] Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 3. SwFlow[3:0] Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 4. PLLFactor[1:0] Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4 LIST OF FIGURES LIST OF TABLES Maxim Integrated ...
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... GPIOData—GPIO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PLLConfig—PLL Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 BRGConfig—Baud-Rate Generator Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DIVLSB—Baud-Rate Generator LSB Divisor Register DIVMSB—Baud-Rate Generator MSB Divisor Register CLKSource—Clock Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 RevID—Revision Identification Register Maxim Integrated 2 C UART with 128-Word FIFOs LIST OF REGISTERS MAX3107 5 ...
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... A = -40NC to +85NC, unless otherwise noted. Typical values MIN TYP 1.71 2.35 1.71 1.65 1.80 220 2 C interface idle 0. 0V, RST all L RST EXT EXT 7 ) ...........81NC ............... 32NC/W JC MAX UNITS 3.6 V 3.6 V 3.6 V 1.95 V 500 FA 1 100 Maxim Integrated ...
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... Input Low Voltage Input High Voltage Input Hysteresis CTS Input Leakage Current RX Pullup Current Input Capacitance GPIO_ OUTPUTS AND INPUTS Output Low Voltage Output High Voltage Maxim Integrated 2 C UART with 128-Word FIFOs = +1.71V to +3.6V, T EXT = +2.5V +25NC.) (Note 2) A SYMBOL CONDITIONS ...
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... Typical values MIN TYP 2 EXT 0. 1 -40NC to +85NC, unless otherwise noted. Typical values MIN TYP 1 0.5 45 4.7 1.3 4.0 0.6 4.7 1.3 4.0 0 MAX UNITS MAX UNITS 4 MHz 35 MHz MHz 100 kHz 400 0.9 Fs 0.9 Maxim Integrated ...
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... Note the total capacitance of either the clock or data line of the synchronous bus in pF. B Maxim Integrated 2 C UART with 128-Word FIFOs = +1.71V to +3.6V, T EXT A = +2.5V +25NC.) (Note 2) ...
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... C Timing Diagram CS t CSS t CSH SCLK t DS DIN DOUT Figure 2. SPI Timing Diagram 10 REPEATED START CONDITION (Sr) t SU:STA Test Circuits/Timing Diagrams STOP CONDITION ( BUF t t HD:STA SU:STO t LOW t CSH t DO START CONDITION (S) Maxim Integrated ...
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... V (V) A GPIO_ OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT (PUSH-PULL 2.5V EXT 0.5 1.0 1.5 Maxim Integrated 2 C UART with 128-Word FIFOs Typical Operating Characteristics = +25NC, unless otherwise noted.) A VOLTAGE A L LDOEN = AGND 18 3.10 3.35 3. SUPPLY CURRENT vs. TEMPERATURE A 140 V = 3.3V A 120 100 ...
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... XIN 2 AGND 23 V EXT MAX3107 18 20 I2C/SPI RTS/CLKOUT 5 CTS LDOEN GPIO3 DOUT/SDA 17 GPIO2 SCLK/SCL GPIO1 CS/A0 15 GPIO0 DIN/ DGND IRQ 13 V RST 12 L SSOP Pin Descriptions FUNCTION 18 with a 1FF 2 C serial Maxim Integrated ...
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... V — — EP Maxim Integrated 2 C UART with 128-Word FIFOs Serial-Data and Address 1 Input. When I2C/SPI is high, DIN/A1 functions as the DIN SPI serial-data input. When I2C/SPI is low, DIN/A1 functions as the A1 I address programming input and connects to DIN/A1 DGND or V Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending ...
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... GPO3Dat GPO2Dat GPO1Dat PreDiv3 PreDiv2 PreDiv1 FRACT3 FRACT2 FRACT1 Div3 Div2 Div1 Div11 Div10 Div9 PLLBypass PLLEn CrystalEn Maxim Integrated BIT 0 RData0 TData0 LSRErrIEn LSRErrInt RTimoutIEn RTimeout XON1IntEn XON1Int GPI0IntEn GPI0Int RxDisabl RST Length0 TimOut0 Hold0 IrDAEn Halt0 TxTrig0 TxFL0 ...
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... FIFO has a defined number of words waiting to be read out or that a known number of vacant FIFO locations are MICROWIRE is a trademark of National Semiconductor Corp. Maxim Integrated 2 C UART with 128-Word FIFOs available and ready to be filled. The transmit FIFO trig- ger generates an interrupt when the transmit FIFO level is above the programmed trigger level ...
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... In 4x rate mode, the CLKOUT frequency is 4x the programmed baud rate. If the fractional portion of the baud-rate generator is used, the clock is not regular and exhibits jitter. MSB PARITY MAJORITY CENTER SAMPLER Line Noise Indication Clocking and Baud-Rate Generation STOP STOP Maxim Integrated ...
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... XIN and XOUT. Connect an external crystal or ceramic oscillator between XIN and XOUT. XOUT CRYSTAL OSCILLATOR XIN Figure 7. Clock Selection Diagram Maxim Integrated 2 C UART with 128-Word FIFOs When an external clock signal is used, this should RECEIVED be connected to XIN. Leave XOUT unconnected. DATA RX Set CLKSource[4]: ClockEn to 1 and CLKSource[1]: CrystalEn select external clocking ...
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... If 4x rate mode is enabled, the actual baud rate on the line is quadruple that of programmed baud rate f (Figure 8). REF ACTUAL BaudRateConfig[5:4] FRACTIONAL 1x, 2x, 4x RATE f RATE REF GENERATOR = 9 + 5/16 = 9.3125 ACTUAL D ACTUAL = DIV + FRACT/ 28,230,000/(16 x 9.3125) ACTUAL = 189463.0872483221476510067114094 baud 2x and 4x Rate Modes BAUD RATE MODES Maxim Integrated ...
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... FlowCtrl[2]: GPIAddr is set to 1, and the address is updated on logic changes at GPIO_. TxFIFO MAX3107 RxFIFO Figure 9. Auto Transceiver Direction Control Maxim Integrated 2 C UART with 128-Word FIFOs Multidrop Mode In the auto data-filtering mode, the MAX3107 auto- matically accepts data that is meant for its address and places this into the receive FIFO, while it discards data that is not meant for its address ...
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... FlowCtrl[0]: AutoRTS. The HALT and RESUME levels determine the threshold levels at which RTS/CLKOUT is asserted and deasserted. HALT and TX TRANSMITTER RTS/CLKOUT ECHO SUPPRESSION RX RECEIVER HOLD LAST CHARACTER Auto Hardware Flow Control AutoRTS Control MAX13431 Maxim Integrated ...
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... IRQEn[7]: CTSIntEn disable CTS interrupts; then ISR[7]: CTSInt is fixed to logic 0 and the host does not receive interrupts from CTS. If CTS is set high during transmission, the MAX3107 completes transmission of the current word and halts transmission afterwards. Maxim Integrated 2 C UART with 128-Word FIFOs STOP HOLD DELAY ...
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... In polled mode, the RevID register can be polled to check whether the MAX3107 is ready for operation. If the controller gets a valid response from RevID, then the MAX3107 is ready for operation. Autosleep Mode Shutdown Mode 2 C/SPI interface, the registers, the FIFOs, Power-Up and IRQ Maxim Integrated ...
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... Figure 13. Simplified Interrupt Structure Maxim Integrated 2 C UART with 128-Word FIFOs enable register bit. These are the IRQEn, LSRIntEn, SpclChrIntEn and STSIntEn registers. When an ISR interrupt is pending (i.e., any bit in ISR is set) and the ISR is subsequently read, the ISR bits and IRQ are cleared ...
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... The SpclChrIEn bit enables IRQ interrupt generation when the SpCharInt interrupt bit is set in the ISR. Set SpclChrIEn bit low to disable IRQ generation from SpCharInt TData5 TData4 TxEmtyIEn TxTrgIEn TData3 TData2 TData1 RxTrgIEn STSIEn SpclChrIEn TData0 0 LSRErrIEn 0 Maxim Integrated ...
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... SpclChrIntEn bits. The SpCharInt interrupt is cleared when the ISR is read. Bit 0: LSRErrlnt The LSRErrInt bit is set high when any LSR bits, which are enabled through the LSRIntEn, are set. This bit is cleared after the ISR is read. Maxim Integrated 2 C UART with 128-Word FIFOs 6 ...
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... Set the ROverrIEn bit high to enable routing the RxOverrun interrupt to LSR[0]. If ROverrIEn is set low, RxOverrun is not routed to LSR[0]. Bit 0: RTimoutlEn Set the RTimoutIEn bit high to enabled routing the RTimeout interrupt to LSR[0]. If RTimoutIEn is set low, the RTimeout is not routed to LSR[0 NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn 0 Maxim Integrated ...
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... The receive FIFO retains the data in it and discards all new data that does not fit into it. The RxOverrun indication is cleared after the LSR is read or the RxFIFO level falls below its maximum. The RxOverrun flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[1]. Maxim Integrated 2 C UART with 128-Word FIFOs ...
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... XON2Int is not routed to the ISR[1]. Bit 0: XON1IntEn The XON1IntEn bit enables routing the SpclCharInt[0]: XON1Int interrupt to ISR[1]. If XON1IntEn is set low (default), the XON1Int is not routed to the ISR[1 MltDrpIntEn BREAKIntEn XOFF2IntEn XOFF1IntEn XON2IntEn XON1IntEn 0 Maxim Integrated ...
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... The XON1Int interrupt bit is set when an XON1 special character is received and special character detection is enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XON1Int interrupt can be routed to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[0]. Maxim Integrated 2 C UART with 128-Word FIFOs ...
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... These interrupts can be selectively routed to the ISR[2] interrupt bit through the STSIntEn[3:0 ClkRdyIntEn — GPI3IntEn ClockReady — GPI3Int GPI2IntEn GPI1IntEn GPI0IntEn GPI2Int GPI1Int GPI0Int Maxim Integrated ...
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... Data still present in the transmit FIFO remains in the TxFIFO. The TX output is set to logic-high after transmission. Bit 0: RxDisabl Set the RxDisabl bit high to disable the receiver so that the receiver stops receiving data. All data present in the receive FIFO remains in the RxFIFO. Maxim Integrated 2 C UART with 128-Word FIFOs 5 4 ...
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... MAX3107 is possible. All register bits are reset to their reset state and all FIFOs are cleared. Once set high, the RST bit must be cleared by writing RST Loopback SpecialChr RxEmtyInv bus stays active during this reset, therefore, communication RxTrigInv FIFORst RST Maxim Integrated ...
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... The Length[1:0] bits configure the length of the words that the transmitter generates and the receiver checks for at the asynchronous TX and RX interfaces (Table 2). Table 1. StopBits Truth Table LCR[2] WORD LENGTH Maxim Integrated 2 C UART with 128-Word FIFOs ForceParity EvenParity Table 2 ...
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... The unit of the HDplxDelay hold time delay is a 1-bit interval, making the delay baud-rate dependent. The maximum delay is 15-bit intervals TimOut5 TimOut4 TimOutO3 Setup1 Setup0 Hold3 TimOut2 TimOut1 TimOut0 Hold2 Hold1 Hold0 Maxim Integrated ...
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... This signals the far-end station to halt transmission. The actual threshold level is calculated as 8 times Halt[3:0]. Hence, the selectable threshold granularity is eight. The resulting level is in the range 120. Maxim Integrated 2 C UART with 128-Word FIFOs ...
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... The RxFIFOLvl register represents the current number of words in the receive FIFO RxTrig1 RxTrig0 TxTrig3 TxFL5 TxFL4 TxFL3 RxFL5 RxFL4 RxFL3 TxTrig2 TxTrig1 TxTrig0 TxFL2 TxFL1 TxFL0 RxFL2 RxFL1 RxFL0 Maxim Integrated ...
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... The AutoRTS bit enables auto RTS flow control by which the MAX3107 sets its RTS/CLKOUT output dependent on the receive FIFO fill level. The FIFO thresholds at which RTS/CLKOUT changes state are set in FlowLvl. See the Auto Hardware Flow Control section for more information. Maxim Integrated 2 C UART with 128-Word FIFOs ...
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... XON2 and XOFF2 special character detection. Receiver compares XON1, XON2, XOFF1, and XOFF2 and 1 1 controls the transmitter accordingly. XON1, XON2, XOFF1, and XOFF2 special character detection Bit5 Bit4 DESCRIPTION Bit3 Bit2 Bit1 Bit0 0 Maxim Integrated ...
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... MODE2[4] and auto software flow control is not enabled, these bits define a special character. If special character detection and software flow control are both enabled, XOFF1 defines the XOFF flow control character. Maxim Integrated 2 C UART with 128-Word FIFOs ...
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... Bit5 Bit4 GP1OD GP0OD GPI1Dat GPI0Dat Bit3 Bit2 Bit1 GP3Out GP2Out GP1Out GPO3Dat GPO2Dat GPO1Dat Bit0 0 0 GP0Out 0 0 GPO0Dat 0 Maxim Integrated ...
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... CLK; PLLIN Figure 14. PLL Signal Path Table 4. PLLFactor[1:0] Selection Guide PLLFactor1 PLLFactor0 Maxim Integrated 2 C UART with 128-Word FIFOs 5 4 PreDiv5 PreDiv4 /PreDiv (Figure 4). PreDiv is an integer that must be in the range 63. CLK f f CLK ...
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... Div[15:8] is the MSB portion of the integer divisor (DIV 4xMode 2xMode FRACT3 Div5 Div4 Div3 Div13 Div12 Div11 FRACT2 FRACT1 FRACT0 Div2 Div1 Div0 Div10 Div9 Div8 Maxim Integrated ...
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... MODE: R BIT 7 NAME Bit7 Bit6 RESET 1 Bit 7–0: Bit[7:0] The RevID register indicates the revision number of the MAX3107 silicon, starting with 0xA1. This can be used during software development. Maxim Integrated 2 C UART with 128-Word FIFOs — ClockEn ...
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... SDA). The interface supports a clock frequency up to 400kHz. SCL and SDA require pullup resistors that are connected to a positive supply C-compatible interface for Interface Maxim Integrated ...
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... I C slave address (Table 5). The address is defined as the 7 MSBs followed by the read/write bit. Set the read/ write bit configure the MAX3107 to read mode. Set the read/write bit configure the MAX3107 to write Maxim Integrated 2 C UART with 128-Word FIFOs S Sr mode ...
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... The master sends the 8-bit register address. 5) The active slave asserts an ACK on the data line only if the address is valid (NACK if not). 6) The master sends a repeated START (Sr). REGISTER ADDRESS DATA BITS - DATA BITS - REGISTER ADDRESS A 8 DATA BITS NA P Single-Byte Read Maxim Integrated ...
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... The addressed slave asserts an ACK on the data line. 4) The master sends the 8-bit register address. 5) The slave asserts an ACK on the data line only if the address is valid (NACK if not). 6) The master sends a repeated START condition. Maxim Integrated 2 C UART with 128-Word FIFOs DEVICE SLAVE ADDRESS - W A ...
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... Figure example of a setup when the controller, transceiver, and the MAX3107 are powered by three different supplies. ENABLE INTERRUPTS CONFIGURE FIFO CONTROL CONFIGURE FLOW CONTROL CONFIGURE GPIOs START COMMUNICATION Interrupts and Polling Logic-Level Translation voltage defines the logic of EXT Maxim Integrated . L ...
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... Program MODE1[2]: TxHiZ high to set high-impedance state. Program MODE1[3]: RTSHiZ high to set RTS/CLKOUT to a high-impedance state. Figure 25 shows an example of connector sharing with a USB transceiver. Maxim Integrated 2 C UART with 128-Word FIFOs 1.8V 2.5V V ...
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... GPIO3 3. EXT LDOEN 2 SPI/I C RTS 10kΩ RX MAX3107 IRQ SPI RST XIN XOUT AGND V18 DGND 1 µ F 100nF MAX3245 T1IN Tx R1OUT Rx T2IN RTS R2OUT CTS T3IN DTR R3OUT DSR R4OUT DCD R5OUT RI 100nF MAX14840 A B Maxim Integrated ...
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... For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 24 SSOP 24 TQFN-EP Maxim Integrated 2 C UART with 128-Word FIFOs ...
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... Maxim Integrated DESCRIPTION specification for the XIN Clock Input in the Electrical IL Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc. Revision History PAGES CHANGED — ...