STM8AF5289TCX STMicroelectronics, STM8AF5289TCX Datasheet
STM8AF5289TCX
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STM8AF5289TCX Summary of contents
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STM8AF5xxx STM8AF6x69/7x/8x/9x/Ax Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C 5.5 V Features ■ Core – Max MHz CPU – Advanced STM8A core with ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8AF52/62xx, STM8AF51/61xx 5.7.4 5.7.5 5.8 Analog to digital converter (ADC ...
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Contents 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 10.3.10 I 10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8AF52/62xx, STM8AF51/61xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 47. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8AF52/62xx, STM8AF51/61xx List of figures Figure 1. STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 49. LQFP 32-pin low profile quad flat package ( ...
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STM8AF52/62xx, STM8AF51/61xx 1 Introduction This datasheet refers to the STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx products with 32 to 128 Kbytes of program memory. In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM, ‘H’ ...
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Description 2 Description The STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx automotive 8-bit microcontrollers described in this datasheet offer from 32 Kbytes to 128 Kbytes of non volatile memory and integrated true data EEPROM. They are referred to as high density STM8A ...
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STM8AF52/62xx, STM8AF51/61xx 3 Product line-up .. Table 2. STM8AF52xx product line-up with CAN Order code Package STM8AF/P52AA LQFP80 (14x14) STM8AF/P528A STM8AF/P52A9 LQFP64 STM8AF/P5289 (10x10) STM8AF/P5269 STM8AF/P52A8 LQFP48 STM8AF/P5288 (7x7) STM8AF/P5268 Table 3. STM8AF62xx product line-up without CAN Order code Package ...
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Product line-up . Table 4. STM8AF/H/P51xx product line-up with CAN Order code Package STM8AF/H/P51AA LQFP80 STM8AF/H/P519A (14x14) STM8AF/H/P518A STM8AF/H/P51A9 STM8AF/H/P5199 LQFP64 STM8AF/H/P5189 (10x10) STM8AF/H/P5179 STM8AF/H/P5169 STM8AF/H/P51A8 STM8AF/H/P5198 LQFP48 STM8AF/H/P5188 (7x7) STM8AF/H/P5178 STM8AF/H/P5168 12/110 High density Data Flash RAM EEPROM program ...
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STM8AF52/62xx, STM8AF51/61xx ² Table 5. STM8AF/H/P61xx product line-up without CAN Order code Package STM8AF/H/P61AA LQFP80 STM8AF/H/P619A (14x14) STM8AF/H/P618A STM8AF/H/P61A9 STM8AF/H/P6199 LQFP64 STM8AF/H/P6189 (10x10) STM8AF/H/P6179 STM8AF/H/P6169 STM8AF/H/P61A8 STM8AF/H/P6198 LQFP48 (7x7) STM8AF/H/P6188 STM8AF/H/P6178 STM8AF/H/P6186 LQFP32 (7x7)/ STM8AF/H/P6176 High density Data 10-bit Flash ...
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Block diagram 4 Block diagram Figure 1. STM8A block diagram Reset Single wire debug interf. Master/slave automatic resynchronization 400 Kbit/s 10 Mbit/s LIN master SPI emul. 1 Mbit channels 1. Legend: ADC: Analog-to-digital converter beCAN: Controller area ...
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STM8AF52/62xx, STM8AF51/61xx 5 Product overview This section is intended to describe the family features that are actually implemented in the products covered by this datasheet. For more detailed information on each feature please refer to the STM8S and STM8A microcontroller ...
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Product overview 5.2 Single wire interface module (SWIM) and debug module (DM) 5.2.1 SWIM The single wire interface module, SWIM, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. The interface can be activated ...
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STM8AF52/62xx, STM8AF51/61xx 5.4.2 Write protection (WP) Write protection in application mode is intended to avoid unintentional overwriting of the memory. The write protection can be removed temporarily by executing a specific sequence in the user software. 5.4.3 Protection of user ...
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Product overview If desired, the temporary unlock mechanism can be permanently disabled by the user through OPT6/NOPT6 option bytes. 5.5 Clock controller The clock controller distributes the system clock coming from different oscillators to the core and the peripherals. It ...
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STM8AF52/62xx, STM8AF51/61xx 5.5.3 128 kHz low-speed internal RC oscillator (LSI) The frequency of this clock is 128 kHz and it is independent from the main clock. It drives the independent watchdog or the AWU wakeup timer. In systems which do ...
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Product overview Table 7. Peripheral clock gating bits (CLK_PCKENR2) 5.6 Low-power operating modes For efficient power management, the application can be put in one of four different low- power modes. You can configure each mode to obtain the best compromise ...
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STM8AF52/62xx, STM8AF51/61xx 5.7 Timers 5.7.1 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. The watchdog timer activity is controlled by the application program or option bytes. Once the watchdog is activated, ...
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Product overview Table 8. Advanced control and general purpose timers Counter Counter Timer width type TIM1 16-bit Up/down 1 to 65536 TIM2 16-bit Up TIM3 16-bit Up TIM1 - advanced control timer This is a high-end timer designed for a ...
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STM8AF52/62xx, STM8AF51/61xx 5.8 Analog to digital converter (ADC) The STM8A products described in this datasheet contain a 10-bit successive approximation ADC with multiplexed input channels, depending on the package. The ADC name differs between the datasheet and ...
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Product overview Detailed feature list: ● Full duplex, asynchronous communications ● NRZ standard format (mark/space) ● High-precision baud rate generator system – Common programmable transmit and receive baud rates ● Programmable data word length ( ...
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STM8AF52/62xx, STM8AF51/61xx 5.9.2 Universal asynchronous receiver/transmitter with LIN support (LINUART) The devices covered by this datasheet contain one LINUART interface. The interface is available on all the supported packages. The LINUART is an asynchronous serial communication interface which supports extensive ...
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Product overview 5.9.3 Serial peripheral interface (SPI) The devices covered by this datasheet contain one SPI. The SPI is available on all the supported packages. ● Maximum speed: 8 Mbit ● Full duplex synchronous transfers ● Simplex synchronous ...
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STM8AF52/62xx, STM8AF51/61xx ● Interrupt: – Successful address/data communication – Error condition – Wakeup from Halt ● Wakeup from Halt on address detection in slave mode 5.9.5 Controller area network interface (beCAN) The beCAN controller (basic enhanced CAN), interfaces the CAN ...
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Product overview 5.10 Input/output specifications The product features four I/O types: ● Standard I/O 2 MHz ● Fast I MHz ● High sink 8 mA, 2 MHz ● True open drain (I To decrease EMI (electromagnetic interference), ...
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STM8AF52/62xx, STM8AF51/61xx 6 Pinouts and pin description 6.1 Package pinouts Figure 3. LQFP 80-pin pinout NRST OSCIN/PA1 OSCOUT/PA2 V SSIO_1 VCAP V DDIO_1 TIM2_CH3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 (HS) PH0 HS) PH1 ( PH2 PH3 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 1. The ...
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Pinouts and pin description Figure 4. LQFP 64-pin pinout OSCIN/PA1 OSCOUT/PA2 TIM2_CH3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines stands for high sink capability. 30/110 ...
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STM8AF52/62xx, STM8AF51/61xx Figure 5. LQFP 48-pin pinout 1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines stands for high sink capability ...
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Pinouts and pin description Figure 6. LQFP/VFQFPN 32-pin pinout 1. HS stands for high sink capability. Table 12. Legend/abbreviation for the pin description table Type Level Output speed Port and control configuration Reset state 32/110 ...
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STM8AF52/62xx, STM8AF51/61xx Table 13. STM8A microcontroller family pin description Pin number Pin name NRST ( PA1/OSCIN PA2/OSCOUT SSIO_1 ...
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Pinouts and pin description Table 13. STM8A microcontroller family pin description (continued) Pin number Pin name REF DDA SSA REF- ...
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STM8AF52/62xx, STM8AF51/61xx Table 13. STM8A microcontroller family pin description (continued) Pin number Pin name PE7/AIN8 PE6/AIN9 PE5/SPI_NSS PC0/ADC_ETR I PC1/TIM1_CH1 I/O ...
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Pinouts and pin description Table 13. STM8A microcontroller family pin description (continued) Pin number Pin name PI4 PI5 PG5 PG6 ...
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STM8AF52/62xx, STM8AF51/61xx 1. In Halt/Active-halt mode, this pin behaves as follows: - The input/output path is disabled the HSE clock is used for wakeup, the internal weak pull-up is disabled the HSE clock is off, the ...
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Memory and register map 7 Memory and register map 7.1 Memory map Figure 7. Register and memory map Table 14. Memory model 128K Flash program memory size 128K 96K 64K 48K 32K 1. If the device contains the super set ...
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STM8AF52/62xx, STM8AF51/61xx 7.2 Register map In this section the memory and register map of the devices covered by this datasheet is described. For a detailed description of the functionality of the registers, refer to the reference manual RM0016. Table 15. ...
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Memory and register map Table 15. I/O port hardware register map (continued) Address Block 0x00 501E 0x00 501F 0x00 5020 Port G 0x00 5021 0x00 5022 0x00 5023 0x00 5024 0x00 5025 Port H 0x00 5026 0x00 5027 0x00 5028 ...
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STM8AF52/62xx, STM8AF51/61xx Table 16. General hardware register map (continued) Address 0x00 50A0 0x00 50A1 0x00 50A2 to 0x00 50B2 0x00 50B3 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 0x00 50C2 0x00 50C3 0x00 50C4 0x00 50C5 0x00 50C6 ...
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Memory and register map Table 16. General hardware register map (continued) Address 0x00 50F3 0x00 50F4 to 0x00 50FF 0x00 5200 0x00 5201 0x00 5202 0x00 5203 0x00 5204 0x00 5205 0x00 5206 0x00 5207 0x00 5208 to 0x00 520F ...
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STM8AF52/62xx, STM8AF51/61xx Table 16. General hardware register map (continued) Address 0x00 5230 0x00 5231 0x00 5232 0x00 5233 0x00 5234 0x00 5235 USART 0x00 5236 0x00 5237 0x00 5238 0x00 5239 0x00 523A 0x00 523B to 0x00 523F 0x00 5240 ...
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Memory and register map Table 16. General hardware register map (continued) Address 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D ...
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STM8AF52/62xx, STM8AF51/61xx Table 16. General hardware register map (continued) Address 0x00 5270 to 0x00 52FF 0x00 5300 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A 0x00 530B 00 ...
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Memory and register map Table 16. General hardware register map (continued) Address 0x00 5320 0x00 5321 0x00 5322 0x00 5323 0x00 5324 0x00 5325 0x00 5326 0x00 5327 0x00 5328 0x00 5329 0x00 532A 0x00 532B 0x00 532C 0x00 532D ...
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STM8AF52/62xx, STM8AF51/61xx Table 16. General hardware register map (continued) Address 0x00 5400 0x00 5401 0x00 5402 0x00 5403 0x00 5404 0x00 5405 0x00 5406 0x00 5407 0x00 5408 to 0x00 541F 0x00 5420 0x00 5421 0x00 5422 0x00 5423 0x00 ...
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Memory and register map Table 16. General hardware register map (continued) Address 0x00 5437 beCAN 0x00 5438 to 0x00 57FF 1. Depends on the previous reset source. 2. Write only register the bootloader is enabled initialized ...
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STM8AF52/62xx, STM8AF51/61xx Table 17. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register label 0x00 7F81 to 0x00 7F8F 0x00 7F90 DM_BK1RE 0x00 7F91 DM_BK1RH 0x00 7F92 DM_BK1RL 0x00 7F93 DM_BK2RE 0x00 7F94 DM_BK2RH 0x00 7F95 DM DM_BK2RL 0x00 7F96 DM_CR1 ...
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Interrupt table 8 Interrupt table Table 19. STM8A interrupt table Priority Source block — Reset Reset — TRAP SW interrupt 0 TLI External top level interrupt 1 AWU Auto-wakeup from Halt Clock 2 Main clock controller controller 3 MISC External ...
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STM8AF52/62xx, STM8AF51/61xx 9 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Each option byte has to be stored twice, ...
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Option bytes Table 20. Option bytes (continued) Option Option Addr. byte name no. 0x00 OPT6 480B TMU 0x00 NOPT6 480C 0x00 OPT7 480D Flash wait states 0x00 NOPT7 480E 0x00 480F 0x00 OPT8 4810 0x00 OPT9 4811 0x00 OPT10 4812 ...
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STM8AF52/62xx, STM8AF51/61xx Table 21. Option byte description Option byte no. OPT0 OPT1 OPT2 Description ROP[7:0]: Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the STM8A microcontroller family reference manual (RM0016) section on ...
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Option bytes Table 21. Option byte description (continued) Option byte no. OPT3 OPT4 OPT5 OPT6 OPT7 OPT8 OPT9 OPT10 OPT11 54/110 Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI ...
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STM8AF52/62xx, STM8AF51/61xx Table 21. Option byte description (continued) Option byte no. OPT12 OPT13 OPT14 OPT15 OPT16 OPT17 Description TMU_KEY 5 [7:0]: Temporary unprotection key 4 Temporary unprotection key: Must be different from 0x00 or 0xFF TMU_KEY 6 [7:0]: Temporary unprotection ...
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Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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STM8AF52/62xx, STM8AF51/61xx 10.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Pin input voltage 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage ...
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Electrical characteristics Table 23. Current characteristics Symbol I Total current into V VDDIO I Total current out of V VSSIO Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...
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STM8AF52/62xx, STM8AF51/61xx 10.3 Operating conditions Table 26. General operating conditions Symbol f Internal CPU clock frequency CPU V V Standard operating voltage DD/ DDIO C EXT capacitor (1) V CAP ESR of external capacitor ESL of external capacitor T Ambient ...
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Electrical characteristics Table 27. Operating conditions at power-up/power-down Symbol VDD V DD Reset release delay t TEMP Reset generation delay Power-on reset V IT+ threshold Brown-out reset V IT- threshold Brown-out reset V HYS(BOR) hysteresis 1. Guaranteed ...
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STM8AF52/62xx, STM8AF51/61xx Table 28. Total current consumption in Run, Wait and Slow mode. General conditions for V apply Symbol Parameter Supply current in (1) I DD(RUN) Run mode Supply current in (1) I DD(RUN) Run mode Supply current ...
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Electrical characteristics Table 29. Total current consumption in Halt and Active-halt modes. General conditions for V = − 40 ° °C unless otherwise stated applied Symbol Parameter Supply current in I DD(H) Halt mode Supply current ...
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STM8AF52/62xx, STM8AF51/61xx Table 31. Programming current consumption Symbol Parameter I Programming current DD(PROG) Table 32. Typical peripheral current consumption V Symbol Parameter I TIM1 supply current DD(TIM1) I TIM2 supply current DD(TIM2) I TIM3 supply current DD(TIM3) I TIM4 supply ...
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Electrical characteristics Current consumption curves Figure 12 to Figure 17 RAM. Figure 12. Typ. I DD(RUN)HSE @ MHz, peripherals = on CPU 2.5 3 3.5 4 4.5 ...
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STM8AF52/62xx, STM8AF51/61xx 10.3.3 External clock sources and timing characteristics HSE external clock An HSE clock can be generated by feeding an external clock signal MHz to the OSCIN pin. Clock characteristics are subject to general operating ...
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Electrical characteristics Table 34. HSE oscillator characteristics Symbol Parameter R Feedback resistor F ( Recommended load capacitance Oscillator trans conductance m (2) t Startup time SU(HSE) 1. The oscillator needs two load capacitors ...
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STM8AF52/62xx, STM8AF51/61xx 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for V High-speed internal RC oscillator (HSI) Table 35. HSI oscillator characteristics Symbol f Frequency HSI HSI oscillator user trimming accuracy ACC HS HSI oscillator accuracy ...
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Electrical characteristics Low-speed internal RC oscillator (LSI) Subject to general operating conditions for V Table 36. LSI oscillator characteristics Symbol f Frequency LSI t LSI oscillator wakeup time su(LSI) 1. Data based on characterization results, not tested in production. Figure ...
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STM8AF52/62xx, STM8AF51/61xx 10.3.5 Memory characteristics Flash program memory/data EEPROM memory General conditions: T Table 37. Flash program memory/data EEPROM memory Symbol Operating voltage V DD (all modes, execution/write/erase) V Operating voltage (code execution) DD Standard programming time (including erase) for ...
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Electrical characteristics Table 39. Data memory Symbol T Temperature for writing and erasing WE Data memory endurance N WE (erase/write cycles) t Data retention time RET 1. The physical granularity of the memory is four bytes, so cycling is performed ...
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STM8AF52/62xx, STM8AF51/61xx 10.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for V unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down ...
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Electrical characteristics 2. Guaranteed by design. 3. Data based on characterization results, not tested in production. Figure 22. Typical V Figure 23. Typical pull-up resistance R 72/110 and four temperatures ...
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STM8AF52/62xx, STM8AF51/61xx Figure 24. Typical pull-up current I 1. The pull- pure resistor (slope goes through 0). Typical output level curves Figure 25 to Figure 34 show typical output level curves measured with output on a single pin. ...
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Electrical characteristics Figure 29. Typ ports) -40°C 1.5 25°C 85°C 1.25 125°C 1 0.75 0.5 0. [mA] OL Figure 31. Typ (standard ...
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STM8AF52/62xx, STM8AF51/61xx 10.3.7 Reset pin characteristics Subject to general operating conditions for V Table 41. NRST pin characteristics Symbol V NRST low-level input voltage IL(NRST) V NRST high-level input voltage IH(NRST) V NRST low-level output voltage OL(NRST) R NRST pull-up ...
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Electrical characteristics Figure 36. Typical NRST pull-up resistance Figure 37. Typical NRST pull-up current I 140 120 100 The reset network shown in must ensure that the level on the NRST pin ...
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STM8AF52/62xx, STM8AF51/61xx Figure 38. Recommended reset pin protection External reset circuit (optional) 10.3.8 TIM and 4 electrical specifications Subject to general operating conditions for V Table 42. TIM and 4 electrical specifications Symbol f ...
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Electrical characteristics SPI interface 10.3.9 Unless otherwise specified, the parameters given in performed under ambient temperature, f conditions. t MASTER Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 43. ...
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STM8AF52/62xx, STM8AF51/61xx Figure 39. SPI timing diagram in slave mode and with CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT ...
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Electrical characteristics Figure 41. SPI timing diagram - master mode 1. Measurement points are at CMOS levels: 0.3 V 80/110 STM8AF52/62xx, STM8AF51/61xx and 0 Doc ID 14395 Rev 9 ...
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STM8AF52/62xx, STM8AF51/61xx 2 10.3. interface characteristics 2 Table 44 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t SDA ...
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Electrical characteristics 10.3.11 10-bit ADC characteristics Subject to general operating conditions for V specified. Table 45. ADC characteristics Symbol f ADC clock frequency ADC V Analog supply DDA V Positive reference voltage REF+ V Negative reference voltage REF- V Conversion ...
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STM8AF52/62xx, STM8AF51/61xx Table 46. ADC accuracy for V Symbol |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Total ...
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Electrical characteristics 10.3.12 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until ...
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STM8AF52/62xx, STM8AF51/61xx Electromagnetic interference (EMI) Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin loading. Table 48. EMI data Symbol Parameter Peak level S EMI SAE EMI level 1. Data based on characterization ...
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... Symbol LU Static latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 86/110 ...
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STM8AF52/62xx, STM8AF51/61xx 10.4 Thermal characteristics In case the maximum chip junction temperature (T operating conditions degrees Celsius, may be calculated using the following equation: Jmax Equation 3 where: is the maximum ambient temperature in ° ...
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Electrical characteristics 10.4.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 52: Ordering information scheme(1) on page The following example shows how to calculate the temperature range needed ...
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STM8AF52/62xx, STM8AF51/61xx 11 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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Package characteristics 11.1 Package mechanical data Figure 44. LQFP 80-pin low profile quad flat package ( Pin 1 identification 1 Table 52. LQFP 80-pin low profile quad flat package mechanical data Dim ...
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STM8AF52/62xx, STM8AF51/61xx Figure 45. LQFP 64-pin low profile quad flat package ( Pin 1 identification 1 Table 53. LQFP 64-pin low profile quad flat package mechanical data Dim ...
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Package characteristics Figure 46. LQFP 64-pin recommended footprint 1. Drawing is not to scale. Dimensions are in millimeters. 92/110 STM8AF52/62xx, STM8AF51/61xx Doc ID 14395 Rev 9 ...
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STM8AF52/62xx, STM8AF51/61xx Figure 47. LQFP 48-pin low profile quad flat package ( Pin 1 identification 1 Table 54. LQFP 48-pin low profile quad flat package mechanical data Dim ...
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Package characteristics Figure 48. LQFP 48-pin recommended footprint 1. Drawing is not to scale. Dimensions are in millimeters. 94/110 STM8AF52/62xx, STM8AF51/61xx Doc ID 14395 Rev 9 ...
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STM8AF52/62xx, STM8AF51/61xx Figure 49. LQFP 32-pin low profile quad flat package ( Pin 1 identification Table 55. LQFP 32-pin low profile quad flat package mechanical data Dim ...
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Package characteristics Figure 50. LQFP 32-pin recommended footprint 1. Drawing is not to scale. Dimensions are in millimeters. 96/110 STM8AF52/62xx, STM8AF51/61xx Doc ID 14395 Rev 9 ...
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STM8AF52/62xx, STM8AF51/61xx Figure 51. VFQFPN 32-lead very thin fine pitch quad flat no-lead package ( Seating plane C Pin # 0.30 Table 56. VFQFPN 32-lead very thin fine pitch quad flat no-lead package mechanical ...
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Ordering information 12 Ordering information Figure 52. Ordering information scheme Example: Product class 8-bit automotive microcontroller Program memory type F = Flash + EEPROM P = FASTROM H = Flash no EEPROM Device family 51 = Silicon rev X, CAN/LIN ...
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... In addition, STM8A application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full-featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code. ...
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... STM8 toolset The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com. This package includes: ST visual develop Full-featured integrated development environment from STMicroelectronics, featuring: ● Seamless integration of C and ASM toolsets ● Full-featured debugger ● ...
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STM8AF52/62xx, STM8AF51/61xx 13.3 Programming tools During the development cycle, STice provides in-circuit programming of the STM8A Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket ...
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Revision history 14 Revision history Table 57. Document revision history Date 31-Jan-2008 22-Aug-2008 102/110 Revision Rev 1 Initial release Added ‘H’ products to the datasheet (Flash no EEPROM). Features on page 1: Updated Memories, management, Communication interfaces pins by 1. ...
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STM8AF52/62xx, STM8AF51/61xx Table 57. Document revision history (continued) Date 22-Aug-2008 16-Sep-2008 Revision Table 35: Removed ACC parameters; amended data and footnotes. Amended data of ‘RAM and hardware Table 37: Updated names and data of N Table 40: Added V OH ...
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Revision history Table 57. Document revision history (continued) Date 01-Jul-2009 104/110 Revision Added ‘STM8AH61xx’ and ‘STM8AH51xx to document header. Updated Features on page 1 temperature, ADC and I/Os). Updated Table 1: Device Updated Kbytes value of program memory in Chapter ...
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STM8AF52/62xx, STM8AF51/61xx Table 57. Document revision history (continued) Date 01-Jul-2009 Revision Removed Table 22: Total current consumption and timing in halt, fast active halt and slow active halt modes at V Added Table 30: Oscillator current consumption Added Table 31: ...
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Revision history Table 57. Document revision history (continued) Date 22-Oct-2009 13-Apr-2010 08-Jul-2010 106/110 Revision Updated Table 1: Device Rev 5 – Added STM8AF5178, STM8AF519A and STM8AF619A. Updated title on cover page. Modified cover page header to clarify the part numbers ...
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STM8AF52/62xx, STM8AF51/61xx Table 57. Document revision history (continued) Date 3&-Jan-2011 Revision Modified references to reference manual, and Flash programming manual in the whole document. Added reference to AEC Q100 standard on cover page. Renamed timer types as follows: – Auto-reload ...
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Revision history Table 57. Document revision history (continued) Date 3&-Jan-2011 18-Jul-2012 108/110 Revision Renamed Fast Active Halt mode to Active-halt mode with regulator on, and Slow Active Halt mode to Active-halt mode with regulator off, updated Section 5.6: Low-power operating ...
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STM8AF52/62xx, STM8AF51/61xx Table 57. Document revision history (continued) Date 18-Jul-2012 Revision Table 20: Option bytes: updated factory default setting for NOPT17; updated footnote 1. Table 22: Voltage characteristics: updated V Table 26: General operating Table 28: Total current consumption in ...
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