TDA8035HN/C1,151 NXP Semiconductors, TDA8035HN/C1,151 Datasheet
TDA8035HN/C1,151
Specifications of TDA8035HN/C1,151
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TDA8035HN/C1,151 Summary of contents
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TDA8035HN Smart card interface Rev. 2.1 — 3 December 2012 1. General description The TDA8035 is the cost efficient successor of the established integrated contact smart card reader IC TDA8024. It offers a high level of security for the card ...
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... NXP Semiconductors Multiplexed status signal using pin OFFN Chip Select digital input for parallel operation of several TDA8035 ICs. 2.2.1 Other HVQFN32 package Compliant with ISO 7816, NDS and EMV 4.2 payment systems 3. Applications Pay TV Electronic payment ...
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... NXP Semiconductors Table 1. Quick reference data DDP DD(INTF) Xtal Symbol Parameter Card supply voltage: pin supply voltage CC V peak-to-peak ripple voltage ripple(p-p) I supply current CC General t deactivation time deact P total power dissipation tot T ambient temperature amb 5. Ordering information Table 2 ...
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... NXP Semiconductors 6. Block diagram V DD(INTF) 100 nF V DD(INTF) CS CMDVCCN EN_5V/3VN EN_1.8VN RSTIN LATCH CLKDIV1 CLKDIV2 HOST INTERFACE I/OUC AUX1UC AUX2UC V DD(INTF) OFFN H Z Fig 1. Block diagram TDA8035HN Product data sheet COMPANY PUBLIC V DDP 100 PORADJ GND REG DDP INTERNAL ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. 7.2 Pin description Table 3. Pin description Symbol Pin Supply I/OUC 1 V DD(INTF) PORADJ 2 V DD(INTF) CMDVCCN 3 V DD(INTF DD(INTF) DD(INTF) CLKDIV1 5 V DD(INTF) CLKDIV2 6 V DD(INTF) EN_5V/3VN 7 V DD(INTF) EN_1 DD(INTF) RSTIN 9 V DD(INTF) ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Supply SBM 17 V DDP DDP DDP SBP 19 V DDP SAP 20 V DDP VUP 21 V DDP RST CLK GNDC 25 - AUX1 AUX2 I DD(INTF) PRESN 30 V DD(INTF) ...
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... NXP Semiconductors 8. Functional description Remark: The ISO 7816 terminology convention has been adhered to throughout this document, and it is assumed that the reader is familiar with this convention. 8.1 Power supply Power supply voltage V All interface signals with the system controller are referenced to V contacts remain inactive during powering up or powering down. ...
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... NXP Semiconductors 8.2 Voltage supervisor Fig 3. The voltage supervisor is used as a power-on reset, and also as supply drop detection during a card session. The threshold of the voltage supervisor is set internally in the IC for V and V DDP pin. As long as V the levels on the command lines are. The inactivity lasts for the duration of t ...
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... NXP Semiconductors Supervisor outputs Supervisor inputs Deep_shutdown IC pins Fig 4. Fig 5. TDA8035HN Product data sheet COMPANY PUBLIC Vth_vddp_Ih Vt vsup X reset X supalarm X X Oscint X Vbg X OFFN X Voltage supervisor V DDP 2.65 V 2.5 V Vth_vddp_hI V 1 REG 1.8 V Vsup 2 Supalarm 3 100 μs analog delay Reset Voltage supervisor All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 8.3 Clock circuitry Fig 6. To generate the card clock CLK, the TDA8035 can either use an external clock provided on XTAL1 pin or a crystal oscillator connected on both XTAL1 and XTAL2 pins. The TDA8035 automatically detects when an external clock is provided on XTAL1. Consequently, there is no need for an extra pin to configure the clock source (external clock or crystal) ...
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... NXP Semiconductors 8.4 I/O circuitry The three data lines I/O, AUX1 and AUX2 are identical. To enter the idle state, both lines (I/O and I/OUC) are pulled HIGH via a 10 k resistor (I and I/OUC I/O is referenced to V The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables the detection of falling edges on the other line, which becomes the slave ...
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... NXP Semiconductors 8.5 CS control The CS (Chip Select) input allows multiple devices to operate in parallel. When CS is high, the system interface signals operate as described. When CS is low, the signals CMDVCCN, RSTIN, CLKDIV1, CLKDIV2, EN_5V/3VN and AUX1UC and AUX2UC are set to high impedance pull-up mode and data is no longer passed to or from the smart card ...
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... NXP Semiconductors 8.7 Activation sequence The following sequence then occurs with crystal oscillator (see CMDVCCN is pulled low (t0) 2. Crystal oscillator start-up time (t0). 3. The internal oscillator changes to its high frequency and DC-to-DC starts 768 I/O, AUX1 and AUX2 are enabled (t 6 ...
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... NXP Semiconductors 8.8 Deactivation sequence When a session is completed, the microcontroller sets the CMDVCCN line to the HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back and ends in the inactive state (see 1. RST goes LOW (t 2. CLK is stopped LOW (t 3. I/O, AUX1 and AUX2 are pulled LOW (t 4 ...
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... NXP Semiconductors 8.10 Fault detection The circuit monitors the following fault conditions: • short-circuit or high current on V • Card removal during transaction • V DDP • overheating. There are two different cases (see 1. CMDVCCN High (outside a card session): OFFN is Low when the card is not in the reader, and High when the card is in the reader ...
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... NXP Semiconductors OFFN PRESN RST VUP Xtal1 Oscint Fig 10. Emergency deactivation sequence (card extraction) PRESN CMDVCCN Fig 11. Behavior of OFFN, CMDVCCN, PRESN and V TDA8035HN Product data sheet COMPANY PUBLIC CLK I high frequency t10 = t11 t12 t13 t14 OFFN tdeb V CC Deactivation caused by cards withdrawal All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 9. Limiting values All card contacts are protected against a short-circuit with any other card contact. Stress beyond the limiting values can damage the device permanently. The values are stress ratings only and functional operation of the device under these conditions is not implied ...
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... NXP Semiconductors 11. Characteristics Table 7. Characteristics 3 3 DDP DD(INTF) XTAL Symbol Parameter Supply voltage V power supply voltage DDP V interface supply voltage DD(INTF) I power supply current DDP I interface supply current DD(INTF) V threshold voltage on pin th(VREG) V REG V hysteresis voltage on pin hys(VREG) V REG ...
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... NXP Semiconductors Table 7. Characteristics 3 3 DDP DD(INTF) XTAL Symbol Parameter VUP (DC-to-DC converter) V HIGH-level output voltage VDDP=3.3V SAP (DC-to-DC converter) V HIGH-level output voltage VDDP=3.3V DC-to-DC converter capacitors C DC/DC converter SAPSAM capacitance C DC/DC converter SBPSBM capacitance C DC/DC converter VUP capacitance [1] Card supply voltage ( ...
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... NXP Semiconductors Table 7. Characteristics 3 3 DDP DD(INTF) XTAL Symbol Parameter I output current o V supply voltage CC V peak-to-peak ripple ripple(p-p) voltage I supply current CC SR slew rate Crystal oscillator (XTAL1 and XTAL2) C external capacitance ext f crystal frequency xtal f crystal frequency on pin ...
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... NXP Semiconductors Table 7. Characteristics 3 3 DDP DD(INTF) XTAL Symbol Parameter t input fall time f(i) Data lines (pins I/O, I/OUC, AUX1, AUX2, AUXIUC, AUX2UC) t delay time d t pull-up pulse width w(pu) f maximum frequency max C input capacitance i Data lines to the card (pins I/O, AUX1, AUX2); (Integrated 10 k pull-up resistor connected to V ...
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... NXP Semiconductors Table 7. Characteristics 3 3 DDP DD(INTF) XTAL Symbol Parameter V HIGH-level output voltage No DC load OH V LOW-level input voltage IL V HIGH-level input voltage IH V hysteresis voltage hys I HIGH-level leakage LH current I LOW-level input current IL R pull-up resistance pu t input rise time ...
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... NXP Semiconductors Table 7. Characteristics 3 3 DDP DD(INTF) XTAL Symbol Parameter V output voltage o I output current o V LOW-level output voltage OL V HIGH-level output voltage rise time r t fall time f f frequency on pin CLK CLK duty cycle SR slew rate Control inputs (pins CS, CMDVCCN, CLKDIV1, CLKDIV2, RSTIN, EN_5V/ 3VN, EN_1.8VN) ...
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... NXP Semiconductors Table 7. Characteristics 3 3 DDP DD(INTF) XTAL Symbol Parameter I output current limit Olim I shutdown current sd Timing t activation time act t deactivation time deact t activation time act t debounce time deb [1] To meet these specifications having a value of 220 nF. [2] The transition time and the duty factor definitions are shown in [3] PRESN and CMDVCCN are active LOW ...
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... NXP Semiconductors 12. Application information (1) Place close to the protected pin with good (low resistive) and straight connection to the main ground (2) Place close to the supply pin with good (low resistive) and straight connection to GNDP (3) Place close to TDA8035´s VCC pin with good connection to GNDC (4) Place close to card connector´ ...
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... NXP Semiconductors 13. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions Unit max 1.00 0.05 0.30 mm nom 0.85 0.02 0.21 0.2 min 0.80 0.00 0.18 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering For all "Surface mount reflow soldering" information for the SOT617 packaging, utilize the following NXP Semiconductors documentation link: http://www.nxp.com/documents/application_note/AN10365.pdf 15. Abbreviations Table 8. Acronym ESD 16. Revision history Table 9. Revision history Document ID Release date TDA8035HN v. 2.1 20121203 • Modifications: • • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4. Clock configuration . . . . . . . . . . . . . . . . . . . . . .10 Table 5. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .17 20. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN32 . . . . . . . . . . . . . . . . .5 Fig 3. Block voltage supervisor . . . . . . . . . . . . . . . . . . . .8 Fig 4. Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9 Fig 5. Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9 Fig 6. Switch external clock . . . . . . . . . . . . . . . . . . . . . .10 Fig 7 ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Protection of the contact smart card . . . . . . . . . 1 2.2 Easy integration into your contact reader . . . . . 1 2.2.1 Other Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 7 8 ...