STA559BWSTR STMicroelectronics, STA559BWSTR Datasheet
STA559BWSTR
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STA559BWSTR Summary of contents
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Features Wide-range supply voltage, 4 Three power output configurations: – 2 channels of ternary PWM ( into 4 Ω PWM output – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA559BW 6.1 Configuration registers (addr 0x00 to 0x05 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 Volume ...
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Contents 6.11 Device status register (addr 0x2D Applications ...
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STA559BW List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA559BW Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STA559BW is an integrated solution of digital audio processing, digital amplifier controls and power output stage to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The ...
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STA559BW 2 Pin connections 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (top view) GND_SUB TEST_MODE VCC_REG GND_REG OUT3B / FFX3B OUT3A / FFX3A 2.2 Pin description Table 2. Pin description Pin Type 1 GND ...
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Pin connections Table 2. Pin description (continued) Pin Type 11 Power 12 GND GND 15 Power I/O 21 Power 22 GND Power ...
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STA559BW 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol V Power supply voltage (pins VCCx Digital supply voltage (pins VDD_DIG PLL supply voltage (pin VDD_PLL Operating junction temperature op ...
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Electrical specifications 3.3 Recommended operating conditions Table 5. Recommended operating condition Symbol V Power supply voltage (VCCxA, VCCxB Digital supply voltage DD_DIG V PLL supply voltage DD_PLL T Ambient temperature amb 3.4 Electrical specifications for the digital section ...
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STA559BW 3.5 Electrical specifications for the power section The specifications given in this section are valid for the operating conditions kHz 384 kHz Table 7. Electrical specifications - power section Symbol Parameter ...
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Electrical specifications Figure 3. Test circuit Duty cycle = 50% 14/67 Low current dead time = MAX(DTr, DTf) +Vcc OUTxY INxY gnd Doc ID 18190 Rev 1 STA559BW OUTxY Vcc (3/4)Vcc (1/2)Vcc (1/4)Vcc t DTr DTf Ω Rload = 8 ...
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STA559BW 3.6 Power on/off sequence Figure 4. Power-on sequence VCC VCC VCC VCC VCC VDD_Dig VDD_Dig VDD_Dig VDD_Dig VDD_Dig XTI XTI XTI XTI XTI Reset Reset Reset Reset Reset ...
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Processing data paths 4 Processing data paths Figure 6 below shows the data processing paths inside STA559BW. The whole processing chain can be considered as two consecutive sections. In the first one, dual-channel processing is implemented and in the second ...
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STA559BW Figure 6. Left and right processing Sampling Sampling frequency=Fs frequency= FIR FIR over over sampling sampling From From I2S input I2S input interface interface x2 x2 FIR FIR over over sampling sampling Sampling ...
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I C bus specification bus specification The STA559BW supports the I slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter ...
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STA559BW 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA559BW acknowledges this and then waits for the byte of internal address. After receiving the internal byte ...
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I C bus specification 5.4.4 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA559BW. The master acknowledges each data byte read and then ...
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STA559BW 6 Register description Note: Addresses exceeding the maximum address number must not be written. Table 8. Register summary Addr Name D7 0x00 CONFA FDRB 0x01 CONFB C2IM 0x02 CONFC OCRB 0x03 CONFD SME 0x04 CONFE SVE 0x05 CONFF EAPD ...
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Register description Table 8. Register summary (continued) Addr Name D7 0x1F A1CF3 0x20 A2CF1 0x21 A2CF2 0x22 A2CF3 0x23 B0CF1 0x24 B0CF2 0x25 B0CF3 0x26 CFUD 0x27 MPCC1 0x28 MPCC2 0x29 DCC1 0x2A DCC2 0x2B FDRC1 0x2C FDRC2 0x2D STATUS ...
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STA559BW The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency ( The relationship between the input clock and the input sample rate is determined by both the MCSx and ...
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Register description Thermal warning recovery bypass Table 13. Thermal warning recovery bypass Bit R/W 5 R/W 1 This bit sets the behavior of the IC after a thermal warning disappears. If TWRB is enabled the device automatically restores the normal ...
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STA559BW Serial audio input interface format Table 16. Serial audio input interface Bit R R/W 0 Serial data interface The STA559BW audio serial input interfaces with standard digital audio components ...
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Register description Table 18. Support serial audio input formats for MSB-first (continued) BICKI Table 19. Supported serial audio input formats for LSB-first BICKI 26/67 SAI [3:0] SAIFB 2 ...
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STA559BW To make the STA559BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that: N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles, where N ...
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Register description Table 22. FFX power output mode Bit R R/W 1 FFX compensating pulse size register Table 23. FFX compensating pulse size bits Bit R ...
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STA559BW 6.1.4 Configuration register D (addr 0x03 SME ZDE 0 1 High-pass filter bypass Table 26. High-pass filter bypass Bit R/W 0 R/W 0 The STA559BW features an internal digital high-pass filter for the purpose of AC coupling. ...
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Register description Biquad coefficient link Table 30. Biquad coefficient link Bit R/W 4 R/W 0 For ease of use, all channels can use the biquad coefficients loaded into the Channel-1 coefficient RAM space by setting the BQL bit to 1. ...
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STA559BW 6.1.5 Configuration register E (addr 0x04 SVE ZCE 1 1 Max power correction variable Table 34. Max power correction variable Bit R/W 0 R/W 0 Max power correction Table 35. Max power correction Bit R/W 1 R/W ...
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Register description PWM speed mode Table 38. PWM speed mode Bit R/W RST 4 R/W 0 Distortion compensation variable enable Table 39. Distortion compensation variable enable Bit R/W RST 5 R/W 0 Zero-crossing volume enable Table 40. Zero-crossing volume enable ...
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STA559BW Output configuration Table 42. Output configuration Bit R R/W 0 Table 43. Output configuration engine selection OCFG[1: Note: To the left of the arrow is the processing channel. When using channel ...
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Register description Figure 9. OCFG = 00 (default value) Figure 10. OCFG = 01 Figure 11. OCFG = 10 34/67 OUT1A OUT1A Half Half Bridge Bridge Channel 1 Channel 1 Half Half Bridge Bridge OUT1B OUT1B OUT2A OUT2A Half Half ...
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STA559BW Figure 12. OCFG = 11 The STA559BW can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always fs) seconds length. The PWM ...
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Register description 2.0 channels, two full-bridges (OCFG = 00) Mapping: FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B FFX4A -> OUT4A FFX4B -> OUT4B Default modulation: FFX1A/1B configured as ternary ...
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STA559BW 2.1 channels, two half-bridges + one full-bridge (OCFG = 01) Mapping: FFX1A -> OUT1A FFX2A -> OUT1B FFX3A -> OUT2A FFX3B -> OUT2B FFX1A -> OUT3A FFX1B -> OUT3B FFX2A -> OUT4A FFX2B -> OUT4B Modulation: FFX1A/1B configured as ...
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Register description 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) Mapping: FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B EAPD -> OUT4A TWARN -> OUT4B Default modulation: ...
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STA559BW Invalid input detect mute enable Table 44. Invalid input detect mute enable Bit R/W 2 R/W 1 Setting the IDE bit enables this function, which looks at the input I mutes if the signals are perceived as invalid. Binary ...
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Register description The PWDN register is used to place the low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, ...
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STA559BW 6.2.1 Mute/line output configuration register (addr 0x06 LOC1 LOC0 0 0 Table 50. Line output configuration LOC[1: Line output is only active when OCFG = 00. In this case LOC determines the line output ...
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Register description 6.2.5 Channel 3 / line output volume (addr 0x0A C3VOL7 C3VOL6 0 1 Table 52. Channel volume as a function of CxVOL CxVOL[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) … 01011111 (0x5F) 01100000 (0x60) 01100001 (0x61) ...
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STA559BW 6.3 Audio preset registers (addr 0x0B and 0x0C) 6.3.1 Audio preset register 1 (addr 0x0B Reserved Reserved 1 0 Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. ...
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Register description Table 55. Audio preset AM switching frequency selection (continued) AMAM[2:0] 101 110 Bass management crossover Table 56. Bass management crossover Bit R R/W 0 Table 57. Bass management ...
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STA559BW 6.4 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 0 Tone control bypass Tone control (bass/treble) can be bypassed on a per channel ...
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Register description Binary output enable registers Each individual channel output can be set to output a binary PWM stream. In this mode output channel is considered the positive output and output B is negative inverse. Table 61. ...
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STA559BW 6.5 Tone control register (addr 0x11 TTC3 TTC2 0 1 Tone control Table 64. Tone control boost/cut as a function of BTC and TTC bits BTC[3:0]/TTC[3:0] 0000 0001 0010 … 0101 0110 0111 1000 1001 … 1100 ...
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Register description 6.6.3 Limiter 2 attack/release rate (addr 0x14 L2A3 L2A2 0 1 6.6.4 Limiter 2 attack/release threshold (addr 0x15 L2AT3 L2AT2 0 1 6.6.5 Description The STA559BW includes two independent limiter blocks. The purpose of ...
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STA559BW reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over limiting can reduce the dynamic range to virtually zero and cause program material to sound ...
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Register description Table 66. Limiter release rate vs LxR bits LxR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Anti-clipping mode Table 67. Limiter attack threshold vs LxAT bits (AC mode) LxAT[3:0] ...
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STA559BW Table 67. Limiter attack threshold vs LxAT bits (AC mode) (continued) LxAT[3:0] 1110 1111 Table 68. Limiter release threshold vs LxRT bits (AC mode) LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 ...
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Register description Table 69. Limiter attack threshold vs LxAT bits (DRC mode) (continued) LxAT[3:0] 1001 1010 1011 1100 1101 1110 1111 Table 70. Limiter release threshold vs LxRT bits (DRC mode) LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 ...
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STA559BW 6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19 C1B23 C1B22 C1B15 C1B14 C1B7 C1B6 0 0 6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) D7 ...
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Register description D7 D6 C4B15 C4B14 C4B7 C4B6 0 0 6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25 C5B23 C5B22 C5B15 C5B14 C5B7 C5B6 ...
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STA559BW Reading a set of coefficients from RAM 1. Write 6-bits of address Write bit Read top 8-bits of coefficient Read middle 8-bits of coefficient ...
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Register description Writing a set of coefficients to RAM 1. Write 6-bits of starting address Write top 8-bits of coefficient Write middle 8-bits of coefficient Write bottom 8-bits of ...
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STA559BW Table 71. RAM block for biquads, mixing, scaling, bass management (continued) Index Index (Hex) (Decimal) 40 0x28 41 0x29 42 0x2A 43 0x2B 44 0x2C 45 0x2D 46 0x2E 47 0x2F 48 0x30 49 0x31 50 0x32 51 0x33 ...
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Register description Coefficients stored in the user defined coefficient RAM are referenced in the following manner: CxHy0 = b 1 CxHy1 = b 2 CxHy2 = -a 1 CxHy3 = -a 2 CxHy4 = b 0 where x represents the ...
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STA559BW 6.8 Variable max power correction registers (addr 0x27 - 0x28 MPCC15 MPCC14 MPCC7 MPCC6 1 1 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place ...
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Register description 6.11 Device status register (addr 0x2D PLLUL FAULT This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a ...
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... PLL output jitter. 7.3 Typical output configuration Figure 18 shows the typical output configuration used for BTL stereo mode. Please contact STMicroelectronics for other recommended output configurations. Figure 18. Output configuration for stereo BTL mode (R OUT1A OUT1B OUT2A OUT2B 22 µ ...
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Figure 19. Applications circuit 1 C14 2 3 100µF 25V 4 C18 5 100nF C21 1µF 25V 6 OUT2B 7 8 OUT2A C23 100nF 9 Vcc 10 OUT1B C29 100nF OUT1A C31 1µF 25V 14 C32 15 ...
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STA559BW 8 Package thermal characteristics Using a double-layer PCB the thermal resistance, junction to ambient, with 2 copper ground areas The dissipated power within the device depends primarily on the supply voltage, load impedance and ...
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Package mechanical data 9 Package mechanical data Figure 21 shows the package outline and Table 72. PowerSSO-36 EPD dimensions Symbol Min A 2.15 A2 2.15 a1 0.00 b 0.18 c 0.23 D 10. ...
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Figure 21. PowerSSO-36 EPD outline drawing h x 45° ...
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Revision history 10 Revision history Table 73. Document revision history Date 17-Dec-2010 66/67 Revision 1 Initial release. Doc ID 18190 Rev 1 STA559BW Changes ...
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... STA559BW Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...