74ALVCH16373DG-T NXP Semiconductors, 74ALVCH16373DG-T Datasheet

no-image

74ALVCH16373DG-T

Manufacturer Part Number
74ALVCH16373DG-T
Description
Latches 3.3V 16-BIT D TRANS LATCH 3-S
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74ALVCH16373DG-T

Product Category
Latches
Rohs
yes
Number Of Circuits
2
Logic Type
TTL
Logic Family
ALVC
Polarity
Non-Inverting
Number Of Output Lines
16
High Level Output Current
- 24 mA
Propagation Delay Time
2.1 ns at 3.3 V
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Package / Case
TSSOP-48
Mounting Style
SMD/SMT
Number Of Input Lines
16
Factory Pack Quantity
2000
Part # Aliases
74ALVCH16373DGG
1. General description
2. Features and benefits
The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for
each latch and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or
pull-down resistors to hold unused inputs.
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state
true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition
the latches are transparent, therefore a latch output will change each time its
corresponding D-input changes.
When LE is LOW, the latches store the information that was present at the nDn inputs at a
set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents
of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Rev. 6 — 10 July 2012
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple V
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50  transmission lines at 85 C
Current drive 24 mA at V
CC
CC
= 3.0 V
and GND pins for minimum noise and ground bounce
Product data sheet

Related parts for 74ALVCH16373DG-T

74ALVCH16373DG-T Summary of contents

Page 1

V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 6 — 10 July 2012 1. General description The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Temperature range Package 40 C to +85 C 74ALVCH16373DL 74ALVCH16373DGG 40 C to +85 C 4. Functional diagram Fig 1. Logic symbol 74ALVCH16373 Product data sheet 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state Name Description SSOP48 plastic shrink small outline package; 48 leads; ...

Page 3

... NXP Semiconductors Fig 2. IEC logic symbol Fig 3. Bus hold circuit 1D0 1LE 1OE Fig 4. Logic diagram 74ALVCH16373 Product data sheet 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 1 1OE 1EN 48 1LE C1 24 2OE 2EN 25 2LE C4 47 1D0 1D1 44 1D2 43 1D3 41 1D4 40 1D5 38 1D6 ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration 74ALVCH16373 Product data sheet 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 74ALVCH16373 1 1OE 1Q0 2 1Q1 3 GND 4 1Q2 5 6 1Q3 1Q4 8 1Q5 9 GND 10 11 1Q6 1Q7 12 2Q0 13 2Q1 14 GND 15 16 2Q2 2Q3 2Q4 ...

Page 5

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE 1, 24 1Q0 to 1Q7 11, 12 2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 ...

Page 6

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

Page 7

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C T amb V HIGH-level input IH voltage V LOW-level input IL voltage V HIGH-level output OH voltage V LOW-level output OL voltage I input leakage current I I OFF-state output ...

Page 8

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply CC current I bus hold LOW current BHL I bus hold HIGH current BHH I bus hold LOW BHLO overdrive current I bus hold HIGH BHHO overdrive current ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Symbol Parameter t disable time dis t pulse width W t set-up time su t hold time h C power dissipation PD capacitance [1] All typical values are measured the same as t and t ...

Page 10

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical output levels that occur with the output load Fig 6. Propagation delay, input (nDn) to data output (nQn) Measurement points are given in V and V are typical output levels that occur with the output load. ...

Page 11

... NXP Semiconductors nDn input nLE input The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data setup and hold times for input (nDn) to input (nLE) Table 8. Measurement points Supply voltage Input 2 2.7 V and < 2 ...

Page 12

... NXP Semiconductors 12. Test information Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 10. Load circuit for measuring switching times Table 9 ...

Page 13

... NXP Semiconductors 13. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...

Page 14

... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date 74ALVCH16373 v.6 20120710 • Modifications: 74ALVCH16373 v.5 20111117 • Modifications: 74ALVCH16373 v.4 20100531 74ALVCH16373 v.3 19990920 74ALVCH16373 v.2 19980629 74ALVCH16373 v.1 ...

Page 16

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... V/3.3 V 16-bit D-type transparent latch; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 18

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Test information ...

Related keywords