74ALVCH16373DG-T NXP Semiconductors, 74ALVCH16373DG-T Datasheet
74ALVCH16373DG-T
Specifications of 74ALVCH16373DG-T
Related parts for 74ALVCH16373DG-T
74ALVCH16373DG-T Summary of contents
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V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 6 — 10 July 2012 1. General description The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Temperature range Package 40 C to +85 C 74ALVCH16373DL 74ALVCH16373DGG 40 C to +85 C 4. Functional diagram Fig 1. Logic symbol 74ALVCH16373 Product data sheet 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state Name Description SSOP48 plastic shrink small outline package; 48 leads; ...
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... NXP Semiconductors Fig 2. IEC logic symbol Fig 3. Bus hold circuit 1D0 1LE 1OE Fig 4. Logic diagram 74ALVCH16373 Product data sheet 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 1 1OE 1EN 48 1LE C1 24 2OE 2EN 25 2LE C4 47 1D0 1D1 44 1D2 43 1D3 41 1D4 40 1D5 38 1D6 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration 74ALVCH16373 Product data sheet 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 74ALVCH16373 1 1OE 1Q0 2 1Q1 3 GND 4 1Q2 5 6 1Q3 1Q4 8 1Q5 9 GND 10 11 1Q6 1Q7 12 2Q0 13 2Q1 14 GND 15 16 2Q2 2Q3 2Q4 ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE 1, 24 1Q0 to 1Q7 11, 12 2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C T amb V HIGH-level input IH voltage V LOW-level input IL voltage V HIGH-level output OH voltage V LOW-level output OL voltage I input leakage current I I OFF-state output ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply CC current I bus hold LOW current BHL I bus hold HIGH current BHH I bus hold LOW BHLO overdrive current I bus hold HIGH BHHO overdrive current ...
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... NXP Semiconductors Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Symbol Parameter t disable time dis t pulse width W t set-up time su t hold time h C power dissipation PD capacitance [1] All typical values are measured the same as t and t ...
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... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical output levels that occur with the output load Fig 6. Propagation delay, input (nDn) to data output (nQn) Measurement points are given in V and V are typical output levels that occur with the output load. ...
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... NXP Semiconductors nDn input nLE input The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data setup and hold times for input (nDn) to input (nLE) Table 8. Measurement points Supply voltage Input 2 2.7 V and < 2 ...
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... NXP Semiconductors 12. Test information Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 10. Load circuit for measuring switching times Table 9 ...
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... NXP Semiconductors 13. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date 74ALVCH16373 v.6 20120710 • Modifications: 74ALVCH16373 v.5 20111117 • Modifications: 74ALVCH16373 v.4 20100531 74ALVCH16373 v.3 19990920 74ALVCH16373 v.2 19980629 74ALVCH16373 v.1 ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... V/3.3 V 16-bit D-type transparent latch; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Test information ...