72245LB25JI IDT, 72245LB25JI Datasheet
72245LB25JI
Specifications of 72245LB25JI
Related parts for 72245LB25JI
72245LB25JI Summary of contents
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... RESET LOGIC IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 PIN CONFIGURATIONS V GND PIN ...
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... IDT72205, 63 from full for IDT72215LB, and 127 from full for IDT72225LB/72235LB/ 72245LB. In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the FIFO is written ...
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... IH, OUT CC 4. Tested with outputs disabled (I = 0). OUT 5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz. 6. For the IDT72205/72215/72225 the typical I = 1.81 + 1.12*f CC1 for the IDT72235/72245 the typical I = 2.85 + 1.30*f CC1 These equations are valid under the following conditions: ° ...
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... NOTES: 1. Industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. All other speed grades are available by special order. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. ...
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... When OE is disabled (HIGH), the Q output data bus high-impedance state. LOAD (LD) The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices con- tain two 12-bit offset registers with data on the inputs, or read on the outputs. When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH transition of the Write Clock (WCLK) ...
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... NOTES Empty Offset (Default Values : IDT72205LB n=31, IDT72215LB n = 63, IDT72225LB/72235LB/72245LB n = 127 Full Offset (Default Values : IDT72205LB m=31, IDT72215LB m = 63, IDT72225LB/72235LB/72245LB m = 127) TM EMPTY FLAG/ (EF) When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full Flag goes LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK SKEW1 RCLK NOTE the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK (first valid write ENS RCLK NOTES: 1. When t minimum specification, t (maximum SKEW2 FRL The Latency Timing applies only at the Empty Boundary (EF = LOW). ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK t DS DATA WRITE ENS t ENH t t SKEW2 RCLK LOW DATA IN OUTPUT REGISTER 0 17 NOTE: 1. When t minimum specification, t (maximum SKEW2 FRL The Latency Timing applies only at the Empty Boundary (EF = LOW). ...
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... RCLK NOTES PAF offset maximum FIFO Depth. Number of data words written into FIFO memory = 256 - for the IDT72205LB, 512 - for the IDT72215LB, 1,024 - for the IDT72225LB, 2,048 - ( for the IDT72235LB and 4,096 - ( for the IDT72245LB. ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK t ENS NOTE: 1. Write to Last Physical Location. RCLK t ENS NOTE: 1. Read from Last Physical Location. WCLK RCLK TM t CLKH Note Figure 15. Write Expansion Out Timing ...
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... WRITE EXPANSION IN ( composite flags by ANDing the Empty Flags of every FIFO, and separately ANDing all Full Flags. Figure 20 demonstrates a 36-word width by using two IDT72205LB/72215LB/72225LB/72235LB/72245LBs. Any word width can be attained by adding additional IDT72205LB/72215LB/72225LB/72235LB/ 72245LBs. Please see the Application Note AN-83. RESET (RS) ...
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... These devices can easily be adapted to applications requiring more than 256/ 512/1,024/2,048/4,096 words of buffering. Figure 21 shows Depth Expansion using three IDT72205LB/72215LB/72225LB/72235LB/72245LBs. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input ...
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... Clock Cycle Time (t Commercial & Industrial Speed in Nanoseconds Commercial & Industrial Low Power 256 x 18 Synchronous FIFO 512 x 18 Synchronous FIFO 1,024 x 18 Synchronous FIFO 2,048 x 18 Synchronous FIFO 4,096 x 18 Synchronous FIFO 2766 drw24 for Tech Support: 408-360-1533 email: FIFOhelp@idt.com ) CLK ...