74ABT574APW-T NXP Semiconductors, 74ABT574APW-T Datasheet

no-image

74ABT574APW-T

Manufacturer Part Number
74ABT574APW-T
Description
Flip Flops OCTAL D 3-S
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74ABT574APW-T

Product Category
Flip Flops
Rohs
yes
Number Of Circuits
1
Logic Family
ABT
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
3.4 ns
High Level Output Current
- 32 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOT-360
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
8
Factory Pack Quantity
2500
Supply Voltage - Min
4.5 V
Part # Aliases
74ABT574APW,118
1. General description
2. Features and benefits
The 74ABT574A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT574A is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The clock input (CP) and output enable input (OE) control gates, control the two
sections of the device independently. The state of each data input (Dn, one set-up time
before the Low-to-High clock transition) is transferred to the Q output of the corresponding
flip-flop.
When OE is Low, the stored data appears at the outputs. When OE is High, the outputs
are in the High-impedance “off” state, which means they do not drive or load the bus.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all
eight 3-State buffers independent of the clock operation.
74ABT574A
Octal D-type flip-flop; 3-state
Rev. 2 — 23 November 2012
74ABT574A is flow-through pinout version of 74ABT374A
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
3-State outputs for bus interfacing
Power-on 3-state
Power-on reset
Common output enable
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
Live insertion/extraction permitted.
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Product data sheet

Related parts for 74ABT574APW-T

74ABT574APW-T Summary of contents

Page 1

Octal D-type flip-flop; 3-state Rev. 2 — 23 November 2012 1. General description The 74ABT574A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT574A is an 8-bit, edge triggered ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +85 C 74ABT574AN 40 C to +85 C 74ABT574AD 40 C to +85 C 74ABT574ADB 74ABT574APW 40 C to +85 C 4. Functional diagram ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning $%7$ *1'  DDD Fig 4. Pin configuration DIP20 and SO20 5.2 Pin description Table 2. Pin description Symbol OE D0, D1, D2, D3, D4, D5, D6, D7 GND CP Q0, Q1, Q2, Q3, Q4, Q5, Q6 74ABT574A Product data sheet  9 && &3 Fig 5. ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Load and read register Load register and disable output [ HIGH voltage level HIGH voltage level one setup time before the HIGH-to-LOW CP transition LOW voltage level LOW voltage level one setup time before the HIGH-to-LOW CP transition; ...

Page 5

... NXP Semiconductors Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter I LOW-level output current OL t/V input transition rise and fall rate T ambient temperature amb 9. Static characteristics Table 6. Static characteristics Symbol Parameter V input clamping voltage HIGH-level output OH voltage ...

Page 6

... NXP Semiconductors Table 6. Static characteristics Symbol Parameter C input capacitance I C output capacitance O [1] For valid test results, do not load data into the flip-flops (or latches) after applying the power. [2] This parameter is valid for any V permitted between V = 2.1 V and V CC [3] Do not test more than one output at a time, and the duration of the test must not exceed one second. ...

Page 7

... NXP Semiconductors 11. Waveforms CP input Qn output and V are typical voltage output levels that occur with the output load Fig 6. Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and maximum clock (CP) frequency Dn input CP input The shaded areas indicate when the input is permitted to change for predictable output performance. ...

Page 8

... NXP Semiconductors OE input Qn output Qn output and V are typical voltage output levels that occur with the output load OL OH Fig 8. 3-state output (Qn) enable and disable times negative V M pulse positive V M pulse Input pulse definition ...

Page 9

... NXP Semiconductors 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 12 ...

Page 12

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... Document ID Release date 74ABT574A v.2 20121123 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74ABT574A v.1 19950522 74ABT574A Product data sheet ...

Page 14

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations ...

Related keywords