74LVC2G08GN,115 NXP Semiconductors, 74LVC2G08GN,115 Datasheet

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74LVC2G08GN,115

Manufacturer Part Number
74LVC2G08GN,115
Description
Logic Gates Dual 2-input AND gate
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC2G08GN,115

Rohs
yes
Factory Pack Quantity
5000
1. General description
2. Features and benefits
The 74LVC2G08 provides a 2-input AND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
74LVC2G08
Dual 2-input AND gate
Rev. 12 — 2 April 2013
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
24 mA output drive (V
CMOS low power consumption
Complies with JEDEC standard:
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

Related parts for 74LVC2G08GN,115

74LVC2G08GN,115 Summary of contents

Page 1

Dual 2-input AND gate Rev. 12 — 2 April 2013 1. General description The 74LVC2G08 provides a 2-input AND gate function. Inputs can be driven from either 3 devices. This feature allows the use of ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74LVC2G08DP 40 C to +125 C 74LVC2G08DC 40 C to +125 C 74LVC2G08GT 40 C to +125 C 74LVC2G08GF 40 C to +125 C 74LVC2G08GD 40 C to +125 C 74LVC2G08GM  ...

Page 3

... NXP Semiconductors 5. Functional diagram 001aah788 Fig 1. Logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74LVC2G08 GND 4 001aae981 Fig 4. Pin configuration SOT505-2 and SOT765-1 74LVC2G08 Product data sheet 1Y 2Y Fig ...

Page 4

... NXP Semiconductors 74LVC2G08 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 GND Functional description [1] Table 4. ...

Page 5

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current ...

Page 6

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C [1] T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage LOW-level output voltage input leakage current ...

Page 7

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage LOW-level output voltage input leakage current I I power-off leakage current V OFF I supply current CC I additional supply current CC [1] All typical values are measured ...

Page 8

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions C power dissipation per gate capacitance [1] Typical values are measured at nominal V [ the same as t and t pd PLH PHL [ used to determine the dynamic power dissipation (P PD  ...

Page 9

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times EXT Fig 9. Test circuit for measuring switching times Table 10 ...

Page 10

... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 13

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version ...

Page 14

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.5 mm terminal 1 index area Dimensions (mm are the original dimensions) (1) Unit max 0.05 0.35 2.1 mm nom 0.5 min 0.00 0.15 1.9 Outline version IEC SOT996-2 Fig 14. Package outline SOT996-2 (XSON8) 74LVC2G08 Product data sheet ...

Page 15

... NXP Semiconductors XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1 terminal 1 index area terminal 1 index area L 1 Dimensions (1) Unit max 0.5 0.05 0.25 1.65 mm nom 0.20 1.60 min 0.00 0.15 1.55 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline ...

Page 16

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1116 Fig 16. Package outline SOT1116 (XSON8) ...

Page 17

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1203 Fig 17. Package outline SOT1203 (XSON8) ...

Page 18

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC2G08 v.12 20130402 • Modifications: For type number 74LVC2G08GD XSON8U has changed to XSON8. ...

Page 19

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 20

... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 21

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Package outline ...

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