72V263L15PF IDT, 72V263L15PF Datasheet

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72V263L15PF

Manufacturer Part Number
72V263L15PF
Description
FIFO
Manufacturer
IDT
Datasheet

Specifications of 72V263L15PF

Part # Aliases
IDT72V263L15PF
FEATURES:
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FUNCTIONAL BLOCK DIAGRAM
*Available on the
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
BGA package only.
Choose among the following memory organizations:
Functionally compatible with the IDT72V255LA/72V265LA and
IDT72V275/72V285 SuperSync FIFOs
Up to 166 MHz Operation of the Clocks
User selectable Asynchronous read and/or write ports (BGA Only)
User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
Pin to Pin compatible to the higher density of IDT72V2103/72V2113
Big-Endian/Little-Endian user selectable byte representation
5V tolerant inputs
Fixed, low first word latency
IDT72V223
IDT72V233
IDT72V243
IDT72V253
IDT72V263
IDT72V273
IDT72V283
IDT72V293
*
*
*
*
* *
ASYW
TRST
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
MRS
TMS
TDO
OW
PRS
TCK
BE
TDI
IP
IW
512 x 18/1,024 x 9
1,024 x 18/2,048 x 9
2,048 x 18/4,096 x 9
4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9
16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9
65,536 x 18/131,072 x 9
(BOUNDARY SCAN)
CONFIGURATION
WRITE CONTROL
JTAG CONTROL
WRITE POINTER
WEN
CONTROL
RESET
LOGIC
LOGIC
LOGIC
BUS
3.3 VOLT HIGH-DENSITY SUPERSYNC II™ NARROW BUS FIFO
512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9
WCLK/WR
*
*
OE
OUTPUT REGISTER
65,536 x 18 or 131,072 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
8,192 x 18 or 16,384 x 9
1,024 x 18 or 2,048 x 9
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
D
INPUT REGISTER
512 x 18 or 1,024 x 9
Q
0
0
-D
RAM ARRAY
-Q
n
n
(x9 or x18)
(x9 or x18)
1
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Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
JTAG port, provided for Boundary Scan function (BGA Only)
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball
Grid Array (BGA) (with additional features)
High-performance submicron CMOS technology
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
OFFSET REGISTER
READ POINTER
LOGIC
CONTROL
FLAG
LOGIC
READ
LD
SEN
RCLK/RD
REN
FEBRUARY 2009
IDT72V223, IDT72V233
IDT72V243, IDT72V253
IDT72V263, IDT72V273
IDT72V283, IDT72V293
RT
RM
ASYR
EF/OR
PAE
FF/IR
PAF
HF
PFM
FSEL0
FSEL1
FWFT/SI
*
4666 drw01
*
DSC-4666/16

Related parts for 72V263L15PF

72V263L15PF Summary of contents

Page 1

... TDI TDO IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...

Page 2

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 DESCRIPTION: The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/ x18 data flow. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • ...

Page 3

... Each FIFO has a data input port (D ) and a data output port (Q n which can assume either an 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) during the Master Reset cycle. The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface ...

Page 4

... FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. ...

Page 5

... Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO. ...

Page 6

... OW Output Width I This pin selects the bus width of the read port. During Master Reset, when OW is LOW, the read port willbe config- ured with a x18 bus width HIGH, the read port will bus width. PAE PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset ...

Page 7

... Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. ASYW (1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW Write Port will select Asynchronous operation ...

Page 8

... I Active Power Supply Current (x18 Input to x18 Output) CC1 (4,7) I Standby Current CC2 : NOTES 1. Industrial temperature range product for 7-5ns and 10ns (IDT72V263/72V273/72V283/72V293 only) are available as standard device. All other speed grades are available by special order. ≤ ≤ 2. Measurements with 0 ≥ ...

Page 9

... NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for 7-5ns and 10ns (IDT72V263/72V273/72V283/72V293 only) are available as standard device. All other speed grades are available by special order. 3. Pulse widths less than minimum values are not allowed. ...

Page 10

... Clock to Asynchronous Programmable Almost-Empty Flag PAEA NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 4. Parameters apply to the BGA package only. ...

Page 11

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels ...

Page 12

... When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations reads are performed after a reset, FF will go LOW after D writes to the FIFO. If the x18 Input or x18 Output bus Width is selected 512 writes for the IDT72V223, 1,024 writes for the IDT72V233, 2,048 writes for the ...

Page 13

... When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations reads are performed after a reset, IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected 513 writes for the IDT72V223, 1,025 writes for the IDT72V233, 2,049 writes for the ...

Page 14

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE IDT72V223 ≠ IDT72V223 IDT72V233 x18 Number of (n+1) to 256 (n+1) to 512 Words in (2) 257 to (512-(m+1)) ...

Page 15

... Bus Width NOTES: 1. When programming the IDT72V293 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72V293 with an output bus width of x9 and input bus width of x18, 4 read cycles will be required total of 6 program/ read cycles will be required for x9 bus width if both the input and output bus widths are set to x9. ...

Page 16

... NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 3. Programmable Flag Offset Programming Sequence (Continued) TM NARROW BUS FIFO ...

Page 17

... Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram of the data input lines D FIFO is configured for an input to output bus width x18, x18 x18 to x18, then the following number of read operations are required: for an output bus width of x18 a total of 2 read operations will be required to read the offset registers for the IDT72V223/72V233/72V243/72V253/72V263/72V273/ 72V283/72V293 ...

Page 18

... IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the ...

Page 19

... REN and WEN must be HIGH before bringing RT LOW. When zero latency is utilized, REN does not need to be HIGH before bringing RT LOW. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup ...

Page 20

... LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + t after the valid RCLK cycle. SKEW WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode. If Asynchronous operation of the Read port has been selected, then WEN must be held active, (tied LOW). READ STROBE & READ CLOCK (RD/RCLK) If Synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK ...

Page 21

... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293 ...

Page 22

... IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293 ...

Page 23

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...

Page 24

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS ASYW, ASYR t RSS FSEL0, FSEL1 t RSS OW RSS BE t RSS RM t RSS PFM t RSS IP t RSS ...

Page 25

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF ...

Page 26

... SKEW1 of WCLK and the rising edge of RCLK is less than HIGH. 3. First data word latency 1 SKEW1 RCLK REF Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) TM NARROW BUS FIFO t CLK t t CLKH CLKL 2 t ...

Page 27

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K NARROW BUS FIFO TM NARROW BUS FIFO 27 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEBRUARY 11, 2009 ...

Page 28

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K NARROW BUS FIFO COMMERCIAL AND INDUSTRIAL 28 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

Page 29

... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293 ...

Page 30

... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293 ...

Page 31

... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293 ...

Page 32

... for the IDT72V283 and for the IDT72V293. 2. All other modes for the IDT72V223 for the IDT72V233 for the IDT72V243 for the IDT72V253 for the IDT72V263 for the IDT72V273 for the IDT72V283 and for the IDT72V293. ...

Page 33

... IDT72V293. In FWFT mode: if x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293 ...

Page 34

... D = maximum FIFO Depth. In IDT Standard mode: if x18 Input or x18 Output bus Width is selected 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293 ...

Page 35

... NOTES IDT Standard mode maximum FIFO depth. If x18 Input or x18 Output bus Width is selected 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293 ...

Page 36

... REN Qn Last Word EF t SKEW WR t CYH t CYC NOTE LOW and WEN = LOW. Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode) TM NARROW BUS FIFO t t ENS ENH FFA t CYC 2 t REF t CYL t ...

Page 37

... FF t SKEW t CYL Last Word W X NOTE LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) WCLK t t ENS ENH WEN EFA ...

Page 38

... CYH CYL FFA FF NOTES LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) TM NARROW BUS FIFO ...

Page 39

... For the x18 Input or x18 Output bus Width: 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36 and 65,536 x 36 For both x9 Input and x9 Output bus Widths: 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,284 x 18, 32,768 x 18, 65,536 x 18 and 131,072 x 18 ...

Page 40

... Dn For the x18 Input or x18 Output bus Width: 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 and 131,072 x 18 For both x9 Input and x9 Output bus Widths: 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9 and 262,144 x 9 ...

Page 41

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K TCK TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions ...

Page 42

... Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V223/72V233/72V243/ 72V253/72V263/72V273/72V283/72V293 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices. TDO T ...

Page 43

... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K Test-Logic 0 Run-Test/ Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. ...

Page 44

... The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ ...

Page 45

... Speed Package NOTES: 1. Industrial temperature range product for 7-5ns and 10ns (IDT72V263/72V273/72V283/72V293 only) are available as standard device. All other speed grades are available by special order. 2. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7-5ns speed grades. 3. Green parts are available. For specific speeds and packages contact you sales office. ...

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