72V851L20TF IDT, 72V851L20TF Datasheet
72V851L20TF
Specifications of 72V851L20TF
Related parts for 72V851L20TF
72V851L20TF Summary of contents
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... IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL PIN CONFIGURATION WENA /LDA 2 WCLKA WENA 1 RSA ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL PIN DESCRIPTIONS The IDT72V801/72V811/72V821/72V831/72V841/72V851's two FIFOs, referred to as FIFO A and FIFO B, are identical in every respect. The following Symbol Name I Data Inputs I A0 ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage with TERM Respect to GND T Storage Temperature STG I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... Programmable Almost-Empty Flag and Programmable Almost-Full Flag NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. AC TEST CONDITIONS In Pulse Levels Input Rise/Fall Times ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL SIGNAL DESCRIPTIONS FIFO A and FIFO B are identical in every respect. The following description explains the interaction of input and output signals for FIFO A. The correspond- ing signal names for FIFO B are provided in parentheses ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL contains four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values ...
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... Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write operations, when Array A (B) is full reads are performed after reset, FFA (FFB) will go LOW after 256 writes to the IDT72V801's FIFO A (B), 512 writes to the IDT72V811's FIFO A (B), 1,024 writes to the IDT72V821's FIFO A (B), 2,048 writes to the IDT72V831's FIFO A (B), 4,096 writes to the IDT72V841's FIFO A (B), or 8,192 writes to the IDT72V851's FIFO A (B) ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL RSA (RSB) RENA1, RENA2 (RENB1, RENB2) WENA1 (WENB1) (1) WENA2/LDA (WENB2/LDB) EFA, PAEA (EFB, PAEB) FFA, PAFA (FFA, PAFA ( NOTES: 1 ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL RCLKA (RCLKB) t ENS RENA1, RENA2 (RENB1, RENB2) EFA (EFB ( OEA (OEB) WCLKA, WCLKB WENA1 (WENB1) WENA2 (WENB2) NOTE: is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time 1 ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL WRITE WCLKA (WCLKB) t SKEW1 ( FFA (FFB) WENA1 (WENB1) WENA2 (WENB2) (If Applicable) RCLKA (RCLKB) t ENH t ENS RENA1 (RENB2) OEA ...
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... NOTES PAF offset. 2. (256-m) words for the IDT72V801, (512-m) words the IDT72V811, (1,024-m) words for the IDT72V821, (2,048-m) words for the IDT72V831, (4,096-m) words for the IDT72V841, or (8,192-m) words for the IDT72V851. is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between 3 ...
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... IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL CLK t CLKH WCLKA (WCLKB) t LDA (LDB) t ENS WENA1 (WENB1 ( PAE OFFSET (LSB) t CLK t CLKH RCLKA (RCLKB) t ENS LDA (LDB) ...
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... WRITE ENABLE/LOAD FFA FULL FLAG FFB Figure 15. Block diagram of the two FIFOs contained in one IDT72V801/72V811/72V821/72V831/72V841/72V851 TM be grounded (see Figure 14). In this configuration, the Write Enable 2/Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. ...
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... DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL TWO PRIORITY DATA BUFFER CONFIGURATION The two FIFOs contained in the IDT72V801/72V811/72V821/72V831/ 72V841/72V851 can be used to prioritize two different types of data shared on a system bus. When writing from the bus to the FIFO, control logic sorts ...
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... WENA2/LDA and WENB2/LDB pins are held HIGH during Reset so that these pins operate as second Write Enables. 2. External logic is used to control the flow of data. Please see the Application Note "DEPTH EXPANSION OF IDT'S SYN- CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details of this configuration. ...