AT93C56AY6-10YH-1.8 Atmel, AT93C56AY6-10YH-1.8 Datasheet

IC EEPROM 2KBIT 2MHZ 8DFN

AT93C56AY6-10YH-1.8

Manufacturer Part Number
AT93C56AY6-10YH-1.8
Description
IC EEPROM 2KBIT 2MHZ 8DFN
Manufacturer
Atmel
Datasheet

Specifications of AT93C56AY6-10YH-1.8

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
2K (256 x 8 or 128 x 16)
Speed
250kHz, 1MHz, 2MHz
Interface
3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UDFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT93C56AY6-10YH-1.8TR
1. Features
2. Description
The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable program-
mable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
(when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the
ORG pin is tied to ground). The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential.
The AT93C56A/66A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-
lead EIAJ SOIC,
Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 packages.
The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before write. The write cycle is only
enabled when the part is in the Erase/Write Enable State. When CS is brought “high”
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part.
The AT93C56A/66A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Low-voltage and Standard-voltage Operation
User-selectable Internal Organization
Three-wire Serial Interface
Sequential Read Operation
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms Max)
High Reliability
Automotive Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP
(MLP 2x3), 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP and 8-ball
dBGA2 Packages
– 2.7 (V
– 1.8 (V
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
CC
CC
= 2.7V to 5.5V)
= 1.8V to 5.5V)
8-lead Ultra Thin mini-MAP (MLP 2x3)
, 8-lead Ultra Lead Frame Land
Three-wire
Serial
EEPROM
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT93C56A
AT93C66A
3378O–SEEPR–11/09

Related parts for AT93C56AY6-10YH-1.8

AT93C56AY6-10YH-1.8 Summary of contents

Page 1

... Description The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable program- mable read-only memory (EEPROM) organized as 128/256 words of 16 bits each (when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential ...

Page 2

Table 2-1. Pin Configurations Pin Name Function CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground VCC Power Supply ORG Internal Organization NC No Connect 3. Absolute Maximum Ratings* Operating Temperature .................................... ...

Page 3

Figure 3-1. Block Diagram Note: When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the ...

Page 4

Table 3-1. Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (DO) OUT C Input Capacitance (CS, SK, DI) IN Note: 1. This parameter is characterized and is not 100% tested. Table 3-2. ...

Page 5

Table 3-3. AC Characteristics Applicable over recommended operating range from TTL Gate and 100 pF (unless otherwise noted) Symbol Parameter SK Clock f SK Frequency t SK High Time SKH t SK Low Time SKL Minimum ...

Page 6

... D – 00XXXXXX Data x 16 Comments Reads data stored in memory, at specified address. Write enable must precede all programming modes. Erases memory location A D – D Writes memory location Erases all memory locations. Valid only 4.5V to 5.5V. CC Writes all memory locations. Valid D – ...

Page 7

... Chip Select (CS) is held high. In this case, the dummy bit (logic “0”) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied ...

Page 8

Timing Diagrams Figure 5-1. Synchronous Data Timing Note: 1. This is the minimum SK period. Table 5-1. Notes: Figure 5-2. READ Timing High Impedance DO AT93C56A/66A 8 Organization Key for Timing Diagrams AT93C56A (2K) I/O x ...

Page 9

Figure 5-3. EWEN Timing Figure 5-4. EWDS Timing Figure 5-5. WRITE Timing HIGH IMPEDANCE DO 3378O–SEEPR–11/09 ... ... ... ... ...

Page 10

Figure 5-6. WRAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC Figure 5-7. ERASE Timing HIGH IMPEDANCE DO AT93C56A/66A ...

Page 11

Figure 5-8. ERAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC 3378O–SEEPR–11/ AT93C56A/66A t CS STANDBY CHECK STATUS BUSY HIGH ...

Page 12

... AT93C56AD3-10DH-1.8 (2) AT93C56AY1-10YU-1.8 (Not recommended for new design) (3) AT93C56AY6-10YH-1.8 (4) AT93C56A-W1.8-11 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. “U” designates Green package + RoHS compliant. 3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish. ...

Page 13

AT93C66A Ordering Information Ordering Code (2) AT93C66A-10PU-2.7 (2) AT93C66A-10PU-1.8 (2) AT93C66A-10SU-2.7 (2) AT93C66A-10SU-1.8 (2) AT93C66AW-10SU-2.7 (2) AT93C66AW-10SU-1.8 (2) AT93C66A-10TU-2.7 (2) AT93C66A-10TU-1.8 (2) AT93C66AU3-10UU-1.8 (3) AT93C66AD3-10DH-1.8 (2) AT93C66AY1-10YU-1.8 (Not recommended for new design) (3) AT93C66AY6-10YH-1.8 (4) AT93C66A-W1.8-11 Notes: 1. For ...

Page 14

Packaging Information 8.1 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L ...

Page 15

JEDEC SOIC e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R 3378O–SEEPR–11/09 ...

Page 16

EIAJ SOIC 1 N Top View TOP VIEW Side View SIDE VIEW Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the ...

Page 17

... Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the device through this pad soldered it should be tied to ground Package Drawing Contact: packagedrawings@atmel.com 3378O–SEEPR–11/ ...

Page 18

Map D E Top View Side View 2325 Orchard Parkway San Jose, CA 95131 R AT93C56A/66A End View A SYMBOL TITLE 8Y1, 8-lead (4.90 x ...

Page 19

TSSOP Pin 1 indicator this corner N Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, ...

Page 20

E PIN 1 BALL PAD CORNER Top View PIN 1 BALL PAD CORNER (d1 (e1) Bottom View 8 Solder Balls 1. This drawing is for general information only. ...

Page 21

ULA PIN # TOP VIEW 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R 3378O–SEEPR–11/ SIDE VIEW SYMBOL ...

Page 22

Revision History Revision No. 3378O 3378N 3378M 3378L 3378K AT93C56A/66A 22 Date Comments 11/2009 Added 8S2 package drawing 1/2009 Updated 8Y6 package drawing 7/2008 Updated Ordering Codes Updated to new template 11/2007 Added ULA package offering Removed DC/Don’t Connect ...

Page 23

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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