74AC109PC_Q Fairchild Semiconductor, 74AC109PC_Q Datasheet

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74AC109PC_Q

Manufacturer Part Number
74AC109PC_Q
Description
Flip Flops Dual J-K Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74AC109PC_Q

Number Of Circuits
2
Logic Family
74AC
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Output Type
Differential
Propagation Delay Time
14 ns
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Supply Voltage - Max
6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-16
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
Supply Voltage - Min
2 V
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
74AC109, 74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
FACT™ is a trademark of Fairchild Semiconductor Corporation
74AC109SC
74AC109SJ
74AC109MTC
74ACT109SC
74AC109MTC
74ACT109PC
I
Outputs source/sink 24mA
ACT109 has TTL-compatible inputs
CC
Number
Order
reduced by 50%
Package
Number
MTC16
MTC16
M16A
M16D
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
.
General Description
The AC/ACT109 consists of two high-speed completely
independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the
clock waveform. The JK design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K inputs together.
Asynchronous Inputs:
Pin Descriptions
J
CP
C
S
Q
1
– LOW input to S
– LOW input to C
– Clear and Set are independent of clock
– Simultaneous LOW on C
D1
D1
1
Package Description
, J
, Q
1
Q and Q HIGH
, S
, C
, CP
2
Pin Names
, K
2
D2
D2
, Q
1
2
, K
1
, Q
2
2
D
D
(Set) sets Q to HIGH level
(Clear) sets Q to LOW level
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
D
and S
Description
D
makes both
www.fairchildsemi.com
March 2007
tm

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74AC109PC_Q Summary of contents

Page 1

... N16E Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram FACT™ trademark of Fairchild Semiconductor Corporation ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops ...

Page 2

... LOW-to-HIGH Transition X = Immaterial ) = Previous Logic Diagram One half shown. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 IEEE/IEC Inputs ...

Page 3

... Output Voltage O T Operating Temperature A ∆ ∆ t Minimum Input Edge Rate, AC Devices: V from 30 ∆ ∆ t Minimum Input Edge Rate, ACT Devices: V from 0.8V to 2.0V ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 Parameter Parameter , V @ 3.3V, 4.5V, 5. 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA – ...

Page 4

... All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5. ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 = +25° ...

Page 5

... Minimum Dynamic OLD (5) Output Current I OHD I Maximum CC Quiescent Supply Current Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 = +25° (V) Conditions Typ. = 0.1V or 4.5 V 1.5 ...

Page 6

... Pulse Width Recovery Time, REC Note: 7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 = +25° 50pF C L (6) V (V) Min. Typ. CC 3.3 125 150 5.0 150 175 3.3 4 ...

Page 7

... Recovery Time, rec Note: 9. Voltage range 5.0 is 5.0V ± 0.5V Capacitance Symbol C Input Capacitance IN C Power Dissipation Capacitance PD ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 = +25° 50pF C L (8) V (V) Min. Typ. Max. CC 5.0 145 210 5.0 4.0 7.0 5.0 3.0 6.0 5.0 2.5 5 ...

Page 8

... Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 Package Number M16A 8 www.fairchildsemi.com ...

Page 9

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 Package Number M16D 9 www.fairchildsemi.com ...

Page 10

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.00±0.10 4.55 0.11 MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 0.65 4.4±0.1 1.45 Package Number MTC16 10 5.90 4.45 7.35 5.00 12° www.fairchildsemi.com ...

Page 11

... Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 Package Number N16E 11 www.fairchildsemi.com ...

Page 12

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world. ActiveArray Bottomless Build it Now CoolFET CROSSVOLT CTL™ Current Transfer Logic™ ...

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