74ACT374MTC_Q Fairchild Semiconductor, 74ACT374MTC_Q Datasheet

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74ACT374MTC_Q

Manufacturer Part Number
74ACT374MTC_Q
Description
Flip Flops Oct D-Type Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74ACT374MTC_Q

Number Of Circuits
8
Logic Family
74ACT
Logic Type
D-Type Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Output Type
Single-Ended
Propagation Delay Time
10 ns
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-20
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
3
Supply Voltage - Min
4.5 V
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
74AC374, 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74AC374SC
74AC374SJ
74AC374MTC
74AC374PC
74ACT374SC
74ACT374SJ
74ACT374MSA
74ACT374MTC
74ACT374PC
I
Buffered positive edge-triggered clock
3-STATE outputs for bus-oriented applications
Outputs source/sink 24mA
See 273 for reset version
See 377 for clock enable version
See 373 for transparent latch version
See 574 for broadside pinout version
See 564 for broadside pinout version with inverted
outputs
ACT374 has TTL-compatible inputs
CC
Number
All packages are lead free per JEDEC: J-STD-020B standard.
Order
and I
OZ
reduced by 50%
Package
Number
MTC20
MSA20
MTC20
M20B
M20D
M20B
M20D
N20A
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
General Description
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are com-
mon to all flip-flops.
Package Description
January 2008
www.fairchildsemi.com

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74ACT374MTC_Q Summary of contents

Page 1

... N20A Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0 General Description The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications ...

Page 2

... When the OE is HIGH, the outputs go to the high imped- ance state. Operation of the OE input does not affect the state of the flip-flops. ©1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0 Logic Symbols IEEE/IEC Truth Table ...

Page 3

... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0 3 www.fairchildsemi.com ...

Page 4

... Input Voltage I V Output Voltage O T Operating Temperature Minimum Input Edge Rate, AC Devices: V from 30 Minimum Input Edge Rate, ACT Devices: V from 0.8V to 2.0V ©1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0 Parameter Parameter , V @ 3.3V, 4.5V, 5. 4.5V, 5. Rating 0.5V to 7.0V 20mA 20mA 0. 0.5V CC ...

Page 5

... All outputs loaded; thresholds on input associated with output under test and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5 (V) Conditions Typ ...

Page 6

... Minimum Dynamic OLD (5) Output Current I OHD I Maximum Quiescent CC Supply Current Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5 (V) Conditions Typ. CC 4.5 V 0.1V or 1.5 ...

Page 7

... Parameter t Setup Time, HIGH or LOW Hold Time, HIGH or LOW Pulse Width, HIGH or LOW W Note: 7. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V ©1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5 50pF L (6) V (V) Min. Typ. Max. CC 3.3 60 110 5.0 ...

Page 8

... Setup Time, HIGH or LOW Hold Time, HIGH or LOW Pulse Width, W HIGH or LOW Note: 9. Voltage range 5.0 is 5.0V 0.5V. Capacitance Symbol Parameter C Input Capacitance IN ©1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5 50pF L (8) V (V) Min. Typ. Max. CC 5.0 100 160 5.0 2.0 8.5 10.0 5.0 2.0 8 ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 14

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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