74VHC112MTC_Q Fairchild Semiconductor, 74VHC112MTC_Q Datasheet

no-image

74VHC112MTC_Q

Manufacturer Part Number
74VHC112MTC_Q
Description
Flip Flops Dual J-K Flip-Flops
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74VHC112MTC_Q

Number Of Circuits
2
Logic Family
74VHC
Logic Type
J-K Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Output Type
Differential
Propagation Delay Time
15 ns
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-16
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
Supply Voltage - Min
2 V
©1995 Fairchild Semiconductor Corporation
74VHC112 Rev. 1.2
74VHC112
Dual J-K Flip-Flops with Preset and Clear
Features
Ordering Information
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
74VHC112M
74VHC112SJ
74VHC112MTC
Order Number
High speed: f
Low power dissipation: I
High noise immunity: V
Power down protection is provided on all inputs
Pin and function compatible with 74HC112
MAX
= 200MHz (Typ.) at V
Package
Number
MTC16
M16D
NIH
M16A
CC
= V
= 2µA (Max.) at T
NIL
= 28% V
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
CC
CC
= 5.0V
A
(Min.)
= 25°C
General Description
The VHC112 is an advanced high speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The VHC112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous
state changes are initiated by the falling edge of the
clock. Triggering occurs at a voltage level of the clock
and is not directly related to transition time. The J and K
inputs can change when the clock is in either state with-
out affecting the flip-flop, provided that they are in the
desired state during the recommended setup and hold
times relative to the falling edge of the clock. The LOW
signal on PR or CLR prevents clocking and forces Q and
Q HIGH, respectively. Simultaneous LOW signals on PR
and CLR force both Q and Q HIGH.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Package Description
www.fairchildsemi.com
May 2007
tm

Related parts for 74VHC112MTC_Q

74VHC112MTC_Q Summary of contents

Page 1

... M16D 74VHC112MTC MTC16 Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. ©1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 General Description = 5.0V The VHC112 is an advanced high speed CMOS device CC fabricated with silicon gate CMOS technology 25° ...

Page 2

... CLR Direct Clear Inputs (Active LOW Direct Preset Inputs (Active LOW Outputs Logic Diagram (One Half Shown) ©1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 Truth Table Inputs PR CLR ...

Page 3

... Operating Temperature OPR Input Rise and Fall Time 3.3V ± 0. 5.0V ± 0. Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 Parameter (1) Parameter 3 Rating –0.5V to +7.0V –0.5V to +7.0V –0. 0.5V CC –20mA ±20mA ±25mA ± ...

Page 4

... LOW Level Input 2.0 IL Voltage 3.0–5.5 V HIGH Level 2.0 OH Output Voltage 3.0 4.5 3.0 4.5 V LOW Level 2.0 OL Output Voltage 3.0 4.5 3.0 4.5 I Input Leakage 0–5.5 IN Current I Quiescent 5.5 CC Supply Current ©1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 (V) Conditions Min. 1.50 0 –50µ 1 2.9 4.4 = –4mA I 2. –8mA I 3. 50µ ...

Page 5

... Minimum Hold Time Minimum Recovery Time REC (CLR CP) Note 3.3 ± 0.3V or 5.0 ± 0.5V. CC ©1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 V (V) Conditions CC = 15pF 3.3 ± 0 50pF 15pF 5.0 ± 0 50pF 15pF 3.3 ± 0.3 ...

Page 6

... Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ©1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 Package Number M16A 6 www.fairchildsemi.com ...

Page 7

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 Package Number M16D 7 www.fairchildsemi.com ...

Page 8

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.00±0.10 4.55 0.11 MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 0.65 4.4±0.1 1.45 Package Number MTC16 8 5.90 4.45 7.35 5.00 12° www.fairchildsemi.com ...

Page 9

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ ...

Related keywords