IC EEPROM 1KBIT 3MHZ 8DIP

 

93C46C-I/P

Manufacturer Part Number93C46C-I/P
DescriptionIC EEPROM 1KBIT 3MHZ 8DIP
ManufacturerMicrochip Technology
93C46C-I/P datasheets

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Specifications of 93C46C-I/P

Format - MemoryEEPROMs - SerialMemory TypeEEPROM
Memory Size1K (128 x 8 or 64 x 16)Speed3MHz
InterfaceMicrowire, 3-Wire SerialVoltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CPackage / Case8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN DESCRIPTIONS
SOIC/PDIP/
Name
MSOP/
TSSOP/DFN
CS
1
CLK
2
DI
3
DO
4
Vss
5
ORG/NC
6
NC
7
V
8
CC
3.1
Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle that is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
). This gives the controlling master
CKL
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become “don't care” inputs waiting for a new Start
condition to be detected.
DS21749H-page 12
SOT-23
Rotated SOIC
5
3
Chip Select
4
4
Serial Clock
3
5
Data In
1
6
Data Out
2
7
Ground
—
8
Organization/93XX46C
No Internal Connection/93XX46A/B
—
1
No Internal Connection
6
2
Power Supply
3.3
Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (T
positive edge of CLK).
) between
CSL
This pin also provides Ready/
during erase and write cycles. Ready/
mation is available on the DO pin if CS is brought high
after being low for minimum Chip Select low time (T
and an erase or write operation has been initiated.
The Status signal is not available on DO if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
Note:
After a programming cycle is complete,
issuing a Start bit and then taking CS low
) and
CKH
will clear the Ready/
3.5
Organization (ORG)
When the ORG pin is connected to V
(x16) memory organization is selected. When the ORG
pin is tied to V
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX46A devices are always (x8) organization and
93XX46B devices are always (x16) organization.
Function
after the
PD
status information
Busy
status infor-
Busy
)
CSL
status from DO.
Busy
or Logic HI, the
CC
or Logic LO, the (x8) memory
SS
 2010 Microchip Technology Inc.

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