74LVT16244BEV-T NXP Semiconductors, 74LVT16244BEV-T Datasheet
74LVT16244BEV-T
Specifications of 74LVT16244BEV-T
Related parts for 74LVT16244BEV-T
74LVT16244BEV-T Summary of contents
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... Type number Package Temperature range 40 C to +85 C 74LVT16244BDL 74LVTH16244BDL 40 C to +85 C 74LVT16244BDGG 74LVTH16244BDGG 40 C to +85 C 74LVT16244BEV 40 C to +125 C 74LVT16244BBX 74LVTH16244BBX Name Description SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm TSSOP48 plastic thin shrink small outline package; ...
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... NXP Semiconductors 4. Functional diagram 1A0 1Y0 47 2 1A1 1Y1 46 3 1A2 1Y2 44 5 1A3 1Y3 43 6 1OE 1 2A0 2Y0 41 8 2A1 2Y1 40 9 2Y2 2A2 38 11 2A3 2Y3 37 12 2OE 48 Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 1. Logic symbol ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVT16244B 74LVTH16244B 1 1OE 2 1Y0 1Y1 3 GND 4 1Y2 5 1Y3 2Y0 2Y1 9 GND 10 2Y2 11 12 2Y3 13 3Y0 3Y1 14 GND 15 3Y2 16 17 3Y3 4Y0 19 4Y1 20 GND 21 22 4Y2 23 4Y3 4OE 24 Fig 3. Pin configuration SOT370-1 (SSOP48) and ...
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... NXP Semiconductors terminal 1 index area (1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad however soldered the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SOT1134-2 (HXQFN60) ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin SOT370-1 and SOT362-1 1OE, 2OE, 1, 48, 25, 24 3OE, 4OE 1Y0 to 1Y3 2Y0 to 2Y3 8, 9, 11, 12 3Y0 to 3Y3 13, 14, 16, 17 4Y0 to 4Y3 19, 20, 22, 23 GND 4, 10, 15, 21, 28, 34, 39 18, 31, 42 ...
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... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter I output current O T storage temperature stg T junction temperature j P total power dissipation tot [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C [1] T amb V input clamping voltage IK V HIGH-level output voltage LOW-level output voltage input leakage current I I power-off leakage current V ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter C input capacitance I C output capacitance O [1] Typical values are measured at V [2] Unused pins GND. CC [3] This is the bus hold overdrive current required to force the input to the opposite logic state. ...
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... NXP Semiconductors 11. Waveforms Measurements points are given in and V are typical voltage output levels that occur with the output load Fig 6. Propagation delay input (nAn) to output (nYn) nOE input nYn output nYn output Measurements points are given in V and V are typical voltage output levels that occur with the output load. ...
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... NXP Semiconductors Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 9 ...
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... NXP Semiconductors 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 0.65 mm ball A1 index area ball A1 1 index area DIMENSIONS (mm are the original dimensions UNIT 1 2 max. 0.3 0.7 0. 0.2 0.6 0.35 OUTLINE VERSION IEC SOT702-1 Fig 11 ...
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... NXP Semiconductors HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 0.5 mm terminal 1 index area A10 terminal 1 index area Dimensions Unit max ...
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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVT_LVTH16244B v.11 20120301 • Modifications: For type number 74LVT16244BBX and 74LVTH16244BBX the sot code has changed to SOT1134-2 ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations ...