VIPER37LE STMicroelectronics, VIPER37LE Datasheet - Page 27

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VIPER37LE

Manufacturer Part Number
VIPER37LE
Description
AC/DC Switching Converters ViperPlus Fixed Freq 800V 30mQ 265 Vac
Manufacturer
STMicroelectronics
Type
Off Line Switcherr
Datasheet

Specifications of VIPER37LE

Product Category
AC/DC Switching Converters
Input / Supply Voltage (max)
23.5 V
Input / Supply Voltage (min)
8.5 V
Switching Frequency
60 kHz
Supply Current
2.5 mA
Operating Temperature Range
- 40 C to + 150 C
Mounting Style
Through Hole
Package / Case
SDIP-10
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 25 C
Number Of Outputs
1
Output Power
25 W

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VIPER37
After the startup time, t
capacitor may not be at its nominal value and the controller interprets this situation as an
overload condition. In this case, the OLP delay helps to avoid an incorrect device shutdown
during the startup phase.
Owing to the above considerations, the OLP delay time must be long enough to bypass the
initial output voltage transient and check the overload condition only when the output voltage
is in steady-state. The output transient time depends on the value of the output capacitor
and on the load.
When the value of the C
ensure enough OLP delay, an alternative compensation network can be used, shown in
Figure 31
Using this alternative compensation network, two poles (f
introduced by the capacitors C
The capacitor C
pole is usually used to compensate the high frequency zero due to the ESR (equivalent
series resistor) of the output capacitance of the flyback converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in
Equation 6
Equation 7
Equation 8
R
The C
Equation 5
instead of C
cases, the loop stability and the correct OLP delay time alike.
FB(DYN)
Figure 31
FB1
is the dynamic resistance seen by the FB pin.
.
capacitor fixes the OLP delay and usually C
can still be used to calculate the OLP delay time but C
, are reported by the equations below:
FB
. Using the alternative compensation network, the user can satisfy, in all
FB
introduces a pole (f
SS
FB
, during which the feedback voltage is fixed at
capacitor calculated for the loop stability is too low and cannot
f
f
Doc ID 022218 Rev 1
PFB
PFB
FB
1
and C
=
=
f
ZFB
2
2
PFB
⋅ π
⋅ π
=
FB1
2
R
C
C
) at a higher frequency than f
FB
FB
FB
and the resistor R
⋅ π
1
(
DYN
C
(
(
R
R
FB
1
1
FB
)
FB
1
+
1
(
DYN
R
R
+
FB
FB
R
FB1
)
FB
1
1
PFB
R
(
DYN
results much higher than C
FB
, f
1
)
)
)
FB1
PFB1
.
FB1
) and one zero (f
Operation description
must be considered
ZB
V
FBlin
and f
, the output
PFB1
ZFB
. This
FB
) are
27/35
.

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