74AC74SC_Q Fairchild Semiconductor, 74AC74SC_Q Datasheet

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74AC74SC_Q

Manufacturer Part Number
74AC74SC_Q
Description
Flip Flops Dl D-Type Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74AC74SC_Q

Product Category
Flip Flops
Number Of Circuits
2
Logic Family
74AC
Logic Type
D-Type Flip-Flop
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-14
Minimum Operating Temperature
- 40 C
Number Of Input Lines
4
Number Of Output Lines
2
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
74AC74, 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Order Number
74AC74SC
74AC74SJ
74AC74MTC
74AC74PC
74ACT74SC
74ACT74SJ
74ACT74MTC
74ACT74PC
I
Output source/sink 24mA
ACT74 has TTL-compatible inputs
CC
All packages are lead free per JEDEC: J-STD-020B standard.
reduced by 50%
Package
Number
MTC14
MTC14
M14A
M14D
M14A
M14D
N14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q)
outputs. Information at the input is transferred to the out-
puts on the positive edge of the clock pulse. Clock trig-
gering occurs at a voltage level of the clock pulse and is
not directly related to the transition time of the positive-
going pulse. After the Clock Pulse input threshold volt-
age has been passed, the Data input is locked out and
information present will not be transferred to the outputs
until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
Package Description
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
Q HIGH
D
D
(Set) sets Q to HIGH level
(Clear) sets Q to LOW level
D
and S
D
makes both Q and
January 2008
www.fairchildsemi.com

Related parts for 74AC74SC_Q

74AC74SC_Q Summary of contents

Page 1

... N14A Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 General Description The AC/ACT74 is a dual D-type flip-flop with Asynchro- nous Clear and Set inputs and complementary (Q, Q) outputs ...

Page 2

... HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Clock Transition Previous Q (Q) before LOW-to-HIGH Transition of Clock 0 0 ©1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 Logic Symbols Inputs ...

Page 3

... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 3 www.fairchildsemi.com ...

Page 4

... V Output Voltage O T Operating Temperature Minimum Input Edge Rate, AC Devices: V from 30 Minimum Input Edge Rate, ACT Devices: V from 0.8V to 2.0V ©1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 Parameter Parameter , V @ 3.3V, 4.5V, 5. 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA –0. 0.5V CC – ...

Page 5

... All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5. ©1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 T +25° ...

Page 6

... Maximum I /Input CCT CC I Minimum Dynamic OLD (5) Output Current I OHD I Maximum Quiescent CC Supply Current Notes: 4. All outputs loaded; thresholds on input associated with output under test. ©1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 T +25° (V) Conditions Typ. 4.5 V 0.1V or 1.5 OUT V – 0.1V 5 ...

Page 7

... Hold Time, HIGH or LOW Pulse Width Recovery Time, C rec Dn Note: 6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. ©1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 T +25° 50pF L (6) V (V) Min. Typ. CC 3.3 100 125 5.0 140 160 3.3 3 ...

Page 8

... Pulse Width Recovery Time, C rec Dn Note: 8. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD ©1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 T +25° (8) V (V) Min. Typ. CC 5.0 145 210 5.0 3.0 5.5 n 5.0 3.0 6.0 n 5.0 4.0 7.5 5 ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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