CD4013BCN_Q Fairchild Semiconductor, CD4013BCN_Q Datasheet
CD4013BCN_Q
Specifications of CD4013BCN_Q
Related parts for CD4013BCN_Q
CD4013BCN_Q Summary of contents
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View © 2002 Fairchild Semiconductor Corporation Features Wide supply voltage range: High noise immunity: 0.45 V ...
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Schematic Diagrams www.fairchildsemi.com Logic Diagram 2 ...
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Absolute Maximum Ratings (Note 3) DC Supply Voltage ( Input Voltage ( Storage Temperature Range ( Power Dissipation ( Dual-In-Line Small Outline Lead Temperature ( ...
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AC Electrical Characteristics pF 200k, unless otherwise noted Symbol Parameter CLOCK OPERATION Propagation Delay Time PHL PLH Transition Time THL TLH Minimum ...
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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M14D 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...