LC75852W-TLM-E ON Semiconductor, LC75852W-TLM-E Datasheet
LC75852W-TLM-E
Specifications of LC75852W-TLM-E
Available stocks
Related parts for LC75852W-TLM-E
LC75852W-TLM-E Summary of contents
Page 1
... Ordering number : EN4828A Overview The LC75852E and LC75852W are 1/2 duty dynamic LCD display drivers. In addition to being able to directly drive LCD panels with segments, they can also control up to four general-purpose output ports. These products also include a key scan circuit which allows them to accept input from keypads with keys ...
Page 2
Allowable Operating Ranges –40 to +85°C, V Parameter Symbol Supply voltage Input high-level voltage Input low-level voltage V IL Recommended external R resistance OSC Recommended external C OSC capacitance ...
Page 3
When stopped with CL at the low level 2. When stopped with CL at the high level Pin Assignment LC75852E, 75852W Figure 1 No. 4828-3/16 ...
Page 4
Block Diagram Pin Functions Pin Pin No. Segment outputs: Used to output the display data that is transmitted over the S1/P1 to S4/ serial data input. Pins S1/P1 to S4/P4 can be used as general-purpose outputs S5 ...
Page 5
Serial Data Input 1. When stopped with CL at the low level 2. When stopped with CL at the high level CCB address......................[42H D90 ...........................Display data S0, S1 ................................Sleep control data K0, K1 ................................Key scan output/segment output selection ...
Page 6
Control Data Functions 1. S0, S1 .................Sleep control data This control data switches the LSI between normal mode and sleep mode. It also sets the key scan output standby states for pins KS1 to KS6. Control data Mode S0 S1 ...
Page 7
Display Data and Output Pin Correspondences Output pin COM1 S1/P1 D1 S2/P2 D3 S3/P3 D5 S4/ D11 S7 D13 S8 D15 S9 D17 S10 D19 S11 D21 S12 D23 S13 D25 S14 D27 S15 D29 S16 ...
Page 8
Serial Data Output 1. When stopped with CL at the low level 2. When stopped with CL at the high level CCB address......................[43H] KD1 to KD30 ......................Key data SA ......................................Sleep acknowledge data Note: If key data is read when DO ...
Page 9
Key Scan Operation 1. Key Scan Timing The key scan period is 375T [s]. The key scan is performed twice to reliably determine the key on/off states, and the LSI detects key data agreement. When the key data agrees, the ...
Page 10
Key Scan during Sleep Mode • The pins KS1 to KS6 are set high or low according to the S0 and S1 control data bits. (See the description of the control data function for details.) • key ...
Page 11
Duty - 1/2 Bias LCD Drive Scheme COM1 COM2 S1 to S45 outputs for segments on COM1 side being lit S1 to S45 outputs for segments on COM2 side being lit S1 to S45 outputs for segments on COM1,COM2 ...
Page 12
Internal Block States during the Reset Period (when RES is low) 1. CLOCK GENERATOR Reset is applied and the basic clock stops. However, the state of the OSC pin (the normal or sleep state) is determined after the control data ...
Page 13
Sample Application Circuit Note: * Since open-drain output, a pull-up resistor is required. Select a value (between 1 and 10 kΩ) that is appropriate for the capacitance of the external wiring so that the waveforms are not ...
Page 14
Notes on Controller Key Data Read Techniques 1. Controller key data reading under timer control • Flowchart • Timing Chart t3 ..................Key scan execution time (800T [s]) when the key scan data for two key scans agrees t4 ..................Key scan ...
Page 15
Controller key data reading under interrupt control • Flowchart • Timing Chart t3 ..................Key scan execution time (800T [s]) when the key scan data for two key scans agrees t4 ..................Key scan execution time (1600T [s]) when the key ...
Page 16
Description When determining key on/off and reading key data, the controller must confirm the state of DO output when CE is low. When DO is low, the controller recognizes that a key has been pressed and reads the key ...