ISL6146AFRZ-T7A Intersil, ISL6146AFRZ-T7A Datasheet - Page 19

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ISL6146AFRZ-T7A

Manufacturer Part Number
ISL6146AFRZ-T7A
Description
Hot Swap & Power Distribution LW VOLT ORING FET CONTRLR 3X3 8LD DFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6146AFRZ-T7A

Product Category
Hot Swap & Power Distribution
Rohs
yes
Product
Controllers & Switches
Current Limit
6 A
Supply Voltage - Max
20 V
Supply Voltage - Min
1 V
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Input / Supply Voltage (max)
20 V
Input / Supply Voltage (min)
1 V
Number Of Channels
1
Supply Current
25 uA
The Figure 1 circuit shown on page 1 is the basic circuit used for
OR-ing voltages >3V to 20V.
The ISL6146A application shown in Figure 47 is the configuration
for OR-ing very low voltages of 1V to 3V. Additionally, this
application shows the utilization of the ADJ input with a single
resistor tied to GND. This provides the user a programmable level
of V
and the GATE output is pulled down to allow for normal voltage
fluctuations in the system.
Notice that in both of these circuits, the EN or EN inputs are
defaulted to enabled and have no current path on/off control.
Failure to do so correctly will result in only body diode conduction
and a resulting fault indication.
The V
to emphasize the Kelvin connection necessary to correctly
monitor the voltage across the FET, and for the VR Vth monitor to
eliminate any stray resistance effects.
The ISL6146C application shown in Figure 48 is limited to the 3V
to 20V V
configuration to utilize the UVLO and OVP inputs and capabilities.
As the V
voltage, the related OR-ing FETs will turn on and stay on until
either the minimum voltage requirement is no longer met or the
V
and maximum programmed voltage levels are done with the
resistor divider on the UVLO and OVP pins. These levels should be
programmed to take into account conduction path losses to the
load in addition to the IC operational constraints.
When using the back-to-back FET configuration, the user must
chose FETs to ensure (2r
tripping the V
IN
OUT
voltage exceeds its programmed maximum. The minimum
VOLTAGE
VOLTAGE
IN
DC - DC
DC - DC
3V-20V
3V-20V
FIGURE 48. TYPICAL ISL6146C APPLICATION DIAGRAM
> V
and V
IN
IN
voltage rises above the minimum programmed
IN
range and must implement the back-to-back FET
before the High Speed (HS) Comparator is activated
IN
OUT
+
+
-
-
- V
to FET and GND to ADJ connections are drawn
OUT
UVLO
OVP
UVLO
OVP
VIN
VIN
> 0.5V when ON fault.
DS(ON)
ISL6146C
ISL6146C
Q1
Q3
GATE
GATE
GND
GND
19
+ PCB IR) I
Q2
Q4
VOUT
VOUT
ADJ
ADJ
FLT
FLT
LOAD
< 0.5V to avoid
+
+
C
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ISL6146
The application diagram in Figure 49 shows the ISL6146A or
ISL6146B utilizing the EN or EN pin as a signalled input to open
or close the conduction path from power supply to load. This
feature can be implemented on OR-ing 1V to 20V but is shown
for OR-ing <3V.
The enable input signaling can be simultaneous across the N+1
number of ISL6146s used.
Although not needed for thermal relief, connect the DFN EPAD
to GND.
SWITCH-OVER CIRCUITS
Switch over applications are different than OR-ing applications in
that, the former are looking for the presence of or a condition of
a preferred supply in order to switch to it. Whereas true OR-ing
consists of a redundant N+1 configuration with no preferred
source.
The following 2 circuits are simple single ISL6146 switchover
circuits optimized for situations particular to the V
voltages relative to each other. Figure 50 shows an ISL6146B
switchover circuit where V
source and V
senses the presence of the preferred voltage supply to a
programmable threshold level that when exceeded, V
passed to the output as V
R1 & R2 program the V
preferred voltage to be passed to the output.
Q3 is necessary if V
from flowing into V
DISTRIBUTED
VOLTAGE
VERY LOW
VERY LOW
FIGURE 49. CONTROLLED ON/OFF APPLICATION DIAGRAM
VOLTAGE
VOLTAGE
(1V-BIAS)
(1V-BIAS)
DC - DC
DC - DC
>3V
BATT
+
+
-
-
could be lesser or greater than V
EXT
BATT
BIAS
BIAS
VIN
VIN
when present. The body diode of Q3
EXT
can ever exceed V
BATT
EXT
ISL6146A/B
ISL6146A/B
level that must be preset for the
Q1
Q3
GATE
GATE
, when present, is the preferred
GND
GND
is disconnected from the output.
Q2
Q4
VOUT
EN/EN
VOUT
EN/EN
ADJ
ADJ
FLT
FLT
EXT
to prevent current
ENABLED
WHEN
SIGNALED
ENABLED
WHEN
SIGNALED
EXT
BATT
. This circuit
EXT
April 26, 2013
and V
is
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FN7667.4
+
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