ISL6146AFRZ-T7A Intersil, ISL6146AFRZ-T7A Datasheet - Page 2

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ISL6146AFRZ-T7A

Manufacturer Part Number
ISL6146AFRZ-T7A
Description
Hot Swap & Power Distribution LW VOLT ORING FET CONTRLR 3X3 8LD DFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6146AFRZ-T7A

Product Category
Hot Swap & Power Distribution
Rohs
yes
Product
Controllers & Switches
Current Limit
6 A
Supply Voltage - Max
20 V
Supply Voltage - Min
1 V
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Input / Supply Voltage (max)
20 V
Input / Supply Voltage (min)
1 V
Number Of Channels
1
Supply Current
25 uA
Block Diagram
Pin Configuration
Pin Descriptions
ISL6146D
ISL6146D
ISL6146A
ISL6146B
ISL6146E
ISL6146C
ISL6146A
MSOP/
VOUT
BIAS
DFN
ADJ
*
VIN
1
2
3
3
4
Connected to BIAS on ISL6146A/B/D/E
Connected to VOUT on ISL6146C
EN ISL6146A/D
EN ISL6146B/E
ISL6146A, ISL6146B, ISL6146D, ISL6146E
SYMBOL
GATE
UVLO
BIAS
GATE
VIN
BIAS
EN
VIN
57mV
19mV
ENABLE
1
2
3
4
+
+
+
Q-PUMP
Gate Drive output to the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically
<1ms. Allows active control of external N-Channel FET gate to perform OR-ing function.
The GATE drive is between V
Connected to the sourcing supply side (OR-ing MOSFET Source), this pin serves as the sense pin to determine the OR’d
supply voltage. The OR-ing MOSFET will be turned off when V
set threshold or the defaulted internal threshold. Range: 0V to 24V
Primary bias pin. Connected to an independent voltage supply greater than or equal to 3V and greater than V
Range: 3.0 to 24V
Programmable UVLO protection to prevent premature turn-on prior to VIN being adequately biased. Range: 0V to 24V
Active high enable input to turn on the FET. Internally pulled low to GND through 2MΩ.
Range: 0V to 24V
REVERSE DETECTION
COMPARATOR
VDS FORWARD
REGULATOR
HIGH SPEED
COMPARATOR
2
*
8
7
6
5
8mA
VOUT
ADJ
FAULT
GND
IN
EPAD on DFN only, connect to GND
+ 7V at V
4A
GATE
(8 LD MSOP/DFN)
ISL6146
IN
TOP VIEW
= 3.3V and V
ISL6146
EN/EN
ISL6146A/B/D/E
FAULT DIAGNOSTIC
1. V
2. GATE - V
3. TEMP > +150°C
4. V
5. V
6. V
7. Gate to Drain and Gate to Source Shorts
DESCRIPTION
+
-
IN
IN
BIAS
IN
IN
+12V at V
V
- V
OR V
< V
IN
REF
becomes lower than V
OUT
< POR (ISL6146A/B/D/E)
OUT
UVLO
GATE
IN
OUT
OVP
VIN
> 570mV
< 220mV (A,B,C only)
ENABLE
IN
< POR (ISL6146C)
= 18V.
1
2
3
4
ISL6146C
UVLO
OVP
OUT
by a value more than the externally
+
-
+
+
ISL6146C
V
8
7
6
5
REF
VOUT
ADJ
FAULT
GND
FLT
IN
April 26, 2013
.
FN7667.4
EN

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