ISL6146AFRZ-T7A Intersil, ISL6146AFRZ-T7A Datasheet - Page 7

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ISL6146AFRZ-T7A

Manufacturer Part Number
ISL6146AFRZ-T7A
Description
Hot Swap & Power Distribution LW VOLT ORING FET CONTRLR 3X3 8LD DFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6146AFRZ-T7A

Product Category
Hot Swap & Power Distribution
Rohs
yes
Product
Controllers & Switches
Current Limit
6 A
Supply Voltage - Max
20 V
Supply Voltage - Min
1 V
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Input / Supply Voltage (max)
20 V
Input / Supply Voltage (min)
1 V
Number Of Channels
1
Supply Current
25 uA
Electrical Specifications
temperature range, -40°C to +125°C. (Continued)
CONTROL AND REGULATION I/O
FAULT OUTPUT
ENABLE UVLO/OVP/ADJ INPUTS
V
V
FWD_FLT_HYS
VthR_hysa
VthR_hysc
VthF_hysb
VthF_hysc
V
V
V
TH(HS100k)
I
t
I
SYMBOL
V
V
FLT_LEAK
t
t
FLT_SINK
EN2GTER
V
TH(HS5k)
FWD_FLT
FWD_VR
FLT_L2H
FLT_H2L
VG_FLTr
VG_FLTf
VthRa
VthFb
VthRc
t
VthFc
OS_HS
t
HSpd
toffs
I
V
V
t
ON
Rs
Rr
Rf
Slow Turn-off Time
Turn-On Current
GATE to V
GATE to V
Reverse Voltage Detection
Rising V
Reverse Voltage Detection
Falling V
Reverse Voltage Detection Response
Time
Amplifier Forward Voltage Regulation
HS Comparator Input Offset Voltage
ADJ Adjust Threshold with 5k to GND
ADJ Adjust Threshold with 100k to GND R
HS Comparator Response Time
V
V
Hysteresis
FAULT Sink Current
FAULT Leakage Current
FAULT Low to High Delay
FAULT High to Low Delay
ISL6146A/D EN Rising Vth
ISL6146A/D EN Vth Hysteresis
ISL6146B/E EN Falling Vth
ISL6146B/E EN Vth Hysteresis
ISL6146C OVP Falling Vth
ISL6146C OVP Vth Hysteresis
ISL6146C UVLO Rising Vth
ISL6146C UVLO Vth Hysteresis
EN/UVLO Rising to GATE Rising Delay
EN/OVP Falling to GATE Rising Delay
IN
IN
to V
to V
OUT
OUT
OUT
OUT
IN
IN
Forward Fault Voltage
Forward Fault Voltage
Threshold
Rising Fault Voltage
Falling Fault Voltage
Threshold
PARAMETERS
7
V
CC
= BIAS = 12V, unless otherwise stated. T
V
C
BIAS = 12V, VG = 0V
BIAS = 12V, VG = 20V
GATE > V
(Does not apply to ISL6146D and ISL6146E)
GATE > V
(Does not apply to ISL6146D and ISL6146E)
V
V
ISL6146 controls voltage across FET V
V
resulting in Id*r
R
V
V
V
BIAS = 18V FAULT = 0.5V, V
FAULT = “V
GATE = V
GATE = V
OUT
OUT
IN
GATE
FWD_VR
OUT
IN
IN
ADJ
ADJ
= V
> V
> V
= 5kΩ to GND
= 100kΩ to GND
rising
falling
> V
ISL6146
= 57nF
BIAS
OUT
OUT
IN
GQP
IN
IN
IN
during static forward operation at loads
FLT_H
, 1ns transition, 5V differential
, GATE is fully on, FLT output is low
, GATE is fully on, FLT output is high
, enabled, FLT output is high.
, enabled, FLT output is low.
to FAULT output is low
= 12V, V
to FAULT output is high
TEST CONDITIONS
DS(ON)
”, V
IN
GATE
> V
< V
OUT
FWD_VR
= 18V to 10V,
IN
A
, V
< V
= +25°C to +85°C. Boldface limits apply over the operating
GATE
OUT
= V
, V
DS
GATE
IN
to
+ V
= V
GQP
GL
(Note 8)
0.57
MIN
320
140
330
580
580
580
580
-14
35
10
11
10
5
0.15
0.04
TYP
440
220
170
450
606
606
+90
606
+90
606
0.7
0.8
1.7
-90
-90
58
57
30
10
19
40
44
10
10
9
1
9
(Note 8)
MAX
560
300
570
631
631
631
631
1.1
80
79
51
28
14
95
10
23
12
12
3
April 26, 2013
FN7667.4
UNITS
mA
mA
mA
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
µA
µs
µs
ns
µs
µs
µs
µs
V

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