LED7708 STMicroelectronics, LED7708 Datasheet
LED7708
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LED7708 Summary of contents
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... LED requirements, resulting in an improved overall efficiency. All the current generators are 40 V-rated, allowing the LED7708 to drive several LEDs in series on each channel. The channels can be put in parallel for higher output current. The brightness of the LEDs is controlled by using the serial interface ...
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... Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.5.9 2/53 Output voltage optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Boost converter loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 External MOSFET control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial interface architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Serial interface internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Internal registers access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Brightness data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Brightness registers (BRTxx DEVCFG0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DEVCFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 GSLAT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CHSEL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 8.5.10 8.5.11 8.6 Dimming options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6.1 8.6.2 8.6.3 8.7 Fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.7.1 8.7.2 8.7.3 8.7.4 8.8 Special function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.8.1 8.8.2 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CHSTA register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Internal registers initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Internal dimming oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Dimming waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Grayscale synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Overtemperature alert and thermal protection . . . . . . . . . . . . . . . . . . . . 44 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 LED short-circuit and open channel faults . . . . . . . . . . . . . . . . . . . . . . . 44 Current generators gain adjust ...
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... Default configuration of internal registers after POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 20. FOSC pin setting options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 21. Function of pins involved in dimming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 22. Dimming synchronization control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 23. Detected faulty conditions Table 24. XFAULT pin behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 25. VFQFPN48 ( 1.0 mm.) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4/53 Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 List of figures Figure 1. Basic application circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connection (through top view Figure 3. Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4. Soft-start waveforms (standalone operation Figure 5. Simplified output regulation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6. Effect of slope compensation on small inductor current perturbation (D>0. Figure 7. Simplified serial interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 8 ...
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... Typical application circuit 1 Typical application circuit Figure 1. Basic application circuit schematic 6/53 Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 2 Pin function Figure 2. Pin connection (through top view) Table 2. Pin description Pin Serial interface (SI) core and digital I/O buffer supply input. Connect to LDO3 VSI external supply (3 V-5 V). Insert a 100 nF bypass ceramic capacitor between this pin and SGND. Connect to the host controller’s supply when possible. ...
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... Driver output (channel) #6. 29 CH7 Driver output (channel) #7. 30 CH8 Driver output (channel) #8. 31 CH9 Driver output (channel) #9. 32 CH10 Driver output (channel) #10. 33 CH11 Driver output (channel) #11. 34 CH12 Driver output (channel) #12. 35 CH13 Driver output (channel) #13. 8/53 Function Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 Table 2. Pin description (continued) Pin 36 CH14 Driver output (channel) #14. 37 CH15 Driver output (channel) #15. 38 CH16 Driver output (channel) #16. 39 AGND Analog ground. Common return for the current generators (channels). Minimum output voltage setting. Multi-level input (high, low, floating or resistor to SGND). ...
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... IOK, XMASK, XVOK, XFLT, FSW, LREN, VDR GATE CSNS CH1 to CH16 CH1 to CH16 Human body model JEDEC JESD22- A114 Parameter Conditions ° ° °C A Doc ID 022698 Rev 1 LED7708 Min. Max. Unit - 40 VIN+0.3 - 3.6 LDO3+0 VSI+0 VIN+0.3 VDR+0 ...
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... LED7708 Table 4. Thermal data (continued) Symbol T Storage temperature range STG Junction-ambient thermal R th,JA resistance 1. Device soldered to the STEVAL-ILL035V1 demonstration board. Parameter Conditions Doc ID 022698 Rev 1 Absolute maximum ratings Min. Max. Unit -50 150 30 °C/W 11/53 ...
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... LE pulse width w,LE T DIN setup time su,DIN T DIN hold time h,DIN T LE setup time su, hold time h,LE 12/53 Conditions VIN, LDO3 and VDR shorted together VDR and VIN shorted together Doc ID 022698 Rev 1 LED7708 Min. Max. Unit 3.6 36 3.0 3.6 V 3.0 5.5 36 3.0 5 200 µA 25 MHz ...
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... LED7708 5 Electrical characteristics ( AMB Table 6. Electrical characteristics Symbol Parameter Supply section LREN turn-on threshold LREN turn-off threshold LREN pull-up current LDO3 undervoltage lockout V UVLO,ON upper threshold LDO3 undervoltage lockout V UVLO,OFF lower threshold V VSI turn-on threshold VSI,ON V VSI turn-off threshold VSI,OFF 3 ...
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... GND CHx R =60 kΩ ISETH VSI = 3.3 V VSI = 5 tied to GND 1.275 MIN V to LDO3 1.105 MIN R =220 kΩ 0.985 VMIN V floating 0.765 MIN Doc ID 022698 Rev 1 LED7708 Min. Typ. Max. Unit 0 LDO3 V 0.4 100 mV 300 30 µA 300 450 µ ...
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... LED7708 Table 6. Electrical characteristics (continued) Symbol Parameter Maximum internal reference voltage for output regulation V DAC,FB Minimum internal reference voltage for output regulation Current generators Maximum output current ΔI accuracy with respect to CHxn (1) nominal value Maximum channel-to- channel output current ΔI (1) CHxy ...
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... CHX TARGET Δ ------------------------------------------------ I = max CHX I TARGET ( ) I I – CHX CHY Δ • -------------------------------------- I = max CHY I TARGET Doc ID 022698 Rev 1 Min. Typ. Max. 3.0 3.2 3.4 6.2 6.4 6.6 7.7 8.0 8.3 200 220 3.86 4. x10 11 11 x10 x10 4 25 125 20 155 • 100 100 LED7708 Unit V mV Hz•Ω MHz °C ...
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... LED7708 6 Block diagram Figure 3. Simplified block diagram Doc ID 022698 Rev 1 Block diagram 17/53 ...
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... Device supply The LED7708 integrates two low drop-out linear regulators to derive the +3.3 V (typ.) main supply and the +5 V supply for the gate driver. The VIN pin is the input terminal for both linear regulators. The output of the 3.3 V LDO is the LDO3 pin, the output of the 5 V LDO is the VDR pin ...
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... LED7708 8 Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter DC Characteristics V VIN pin input voltage range VIN V LDO pin input voltage range LDO3 V VDR pin input voltage range VDR V Channel voltage range CHx V Serial interface supply voltage VSI I Channel continuous current ...
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... Anyway, after the POR, the DEN (device enable) bit of the internal DEVCFG0 control register is low (default value) and the device is off. The soft-start sequence takes place as soon as this bit is asserted. If the LED7708 is set to operate in standalone, the soft-start procedure takes place in two steps (Figure 4): 1 ...
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... The device is turned off by clearing the DEN bit of the DEVCFG0 register. The content of most of the internal registers is not cleared acting on the DEN bit. The LREN pin can be also used to turn the device on and off whenever the internal 3.3 V LDO is used to supply the LED7708 (POR). In this case the content of the internal registers is lost. 8.3 ...
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... The algorithm can also manage faulty conditions that may occur on the LED array (open channels and LED short-circuit) in order to prevent excessive power dissipation. The LED7708 has been designed to interface with other slave devices and can provide them with the correct LED supply voltage by extending the above mentioned output voltage optimization ...
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... R1 and R2 are the resistors of the divider connected to the output rail and V reference voltage at the VFB pin. The LED7708 regulates the output voltage in order to optimize the overall efficiency and this, it needs to read the voltage drop across the active current generators. Unfortunately, in some cases (e ...
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... Equation 6 24/ Σ max ( V ) LED Equation 4 and – V BOOST middle , VFB ⋅ --------------------------------------------------------------- VFB V BOOST MAX , ≤ --------------------------------- - 100μ FSW f SW Doc ID 022698 Rev 1 LED7708 spread F . BOOST,middle R 1 Figure 4, COMP pin). Equation 6: ...
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... The minimum pulse width which allows the synchronizing pulses to be detected is 270 ns (typ.). The SYNC pin is a synchronization output and provides a 35% (typ.) duty cycle clock when the LED7708 is set as master or a replica of the FSW pin when it is set as slave used to connect multiple devices in a daisy chain configuration or to synchronize other switching converters running in the system with the LED7708 ...
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... External MOSFET control The LED7708 employs an external MOSFET as the power switch for the boost converter. The internal gate driver is capable of sourcing and sinking and it is supplied through the VDR pin, internally connected to the +5 V LDO µF decoupling capacitor, connected between the VDR pin and PGND, is highly recommended ...
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... The LED-driving section consists of 16 current generators connected to the internal control logic. Each channel can sustain and sink mA. The brightness of the LEDs connected to the LED7708 is controlled by switching the current between a maximum value (on-phase) and a minimum one (off-phase given dimming frequency (PWM control) ...
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... ISETL pin must be connected to the device supply rail (LDO3). The current generators of the LED7708 have been designed to be grouped (i.e. connected in parallel) if required by the application. For stability reasons, the parallelization of the current generators should be done when the programmed current is above 40 mA per channel ...
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... Serial interface architecture The LED7708 is equipped with a 4-wire serial interface (SI) to allow full control of its functionalities by the host controller. The LED7708 uses four pins (DIN, DOUT, DCLK and LE) to connect itself to the serial bus. The serial interface supports a data clock frequency MHz ...
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... Recommended operating conditions 8.5.3 Internal registers access The LED7708 is capable of supporting different data formats to satisfy different application needs. The control registers are accessed one at a time by using 16-bit read/write operations, while the brightness registers can be loaded in sequence (16x16-bit single shot (1x256-bit). An additional data format (1x192-bit) allows data flow optimization when only 12 bits are used for brightness control ...
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... The LE is managed to encode two serial keys: one for the so called “data latch” operation and another to encode the final “global latch” operation. Therefore, a complete brightness data transfer to the LED7708 consists of 15 “data latch” operations followed by a single “global latch” operation. ...
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... The brightness registers BRT01:BRT16 are simultaneously loaded at the end of a single 192-bit single write operation. This option is similar to the 1x256-bit format but optimizes the serial bus communication when 12 bits only are used for the brightness control. Figure 11. 192-bit data format, write operation to the brightness registers 32/53 Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 Normally, the serial data coming from the DIN pin is clocked out at the DOUT pin. Optionally, the LED7708 can continuously transmit the status of the control registers when the continuous status reading (CSRD) bit of the DEVCFG0 register is asserted. In this case the device replaces (with a 16-clock-cycle delay) the received brightness data stored in the FIFO with the CHSTA, CHSEL, LATENCY, DEVCFG0 and DEVCFG1 content ...
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... Destination register address R FIFO loaded into DEVCFG0 1= FIFO loaded into DEVCFG1 (†) In order to prevent damage to the device or to the external circuitry, these bits are locked when the DEN bit of DEVCFG0 is asserted. Doc ID 022698 Rev 1 LED7708 Description Table 17). ...
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... LED7708 8.5.7 DEVCFG1 register Table 15. DEVCFG1 register Bit Position ADJ0 0 ADJ1 1 ADJ2 2 ADJ3 3 ADJ4 4 ADJ5 5 CGRS 6 LAT16 7 LAT17 8 BDFS 9 BRLS 10 DTIN 11 DASS 12 DSYS† 13 CSRD 14 DEST 15 Recommended operating conditions Attribute Default R/W 0 R/W 0 R/W 0 Current gain adjust R/W 0 R/W 0 R/W 0 Current gain range selector 0= range 1 selected ...
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... The GSLAT register is a write-only register and stores the 16 less significant bits of the dimming period latency. The additional two most significant bits are located in the DEVCFG1 register (LAT16 and LAT17 bits). Thanks to the 18-bit wide latency, the LED7708 is capable of supporting down to 20% of scanning waveform (see options for details) ...
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... LED7708 8.5.9 CHSEL register The CHSEL register is a readable/writable configuration register. Every bit of this register allows the user to enable/disable the channels. Independent control of the channels (e.g. scrolling backlight or phase shift) can be achieved by acting on this register. Table 17. CHSEL register Bit Position ...
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... Doc ID 022698 Rev 1 LED7708 Meaning sequence Value (binary) ...
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... Once the dimming control mode has been chosen through the GSME bit, the source of the clock for the PWM generation (grayscale clock) must be selected. The LED7708 can use either an external clock source or its internal high-frequency oscillator. 8.6.1 Internal dimming oscillator The LED7708 has a programmable oscillator dedicated to the dimming circuitry ...
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... The GSSY pin is set as input. The ongoing dimming sequence is reset as soon rising edge on the GSSY input is detected; a new latency+dimming cycle is triggered by the falling edge on this pin. Figure 12. Dimming signals and synchronization 40/ OSC f DIM N 2 Function 21. Dimming sync selector (locked if DEN is asserted) Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 8.6.2 Dimming waveforms Normal dimming mode In normal timing mode the basic cycle is represented by a latency period followed by a dimming period starting with the on-phase (current generators active). This option is selected by clearing the DTIN (dimming timing inversion) bit of the DEVCGF1 register. Figure 13. Normal timing mode waveforms ...
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... Recommended operating conditions 8.6.3 Grayscale synchronization Grayscale sync (GSSY) used as synchronization output When the DSYS bit of the DEVCFG1 register is set low, the GSSY pin of the LED7708 is set as output. A 4xT GSC dimming cycle (latency followed by a dimming period). Figure 15. Dimming waveform and GSSY output pulse ...
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... LED7708 8.7 Fault management The LED7708 includes some protection to prevent damage to itself and to the backlight. In order to satisfy these requirements, the following protection has been implemented: Table 23. Detected faulty conditions Boost output overvoltage (OV) External MOSFET overcurrent (OC) Excessive channel voltage (LED short-circuit) Overtemperature protection ...
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... Recommended operating conditions Equation 16 Once the voltage at the VFB pin has crossed the related threshold, the LED7708 shuts down, the CFP (critical fault protection) flag of the DEVCFG0 register is asserted, the XFLT pin is set low and the condition is latched. Normal operation is restored by toggling the DEN bit of the DEVCFG0 register or by performing a POR ...
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... This situation can induce excessive power dissipation on the other channels (high- voltage drop for a long period). To prevent this, the LED7708 automatically forces the “probably open channel” to remain on (regardless of its programmed status) until the maximum output voltage has been reached (confirmation of open channel fault) or the output current has been recovered ...
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... The content of the DEVCFG0, DEVCFG1, CHSEL, CHSTA and GSLAT is automatically loaded into the FIFO after the brightness data has been moved to the buffer. This feature is supported in 1x1256-bit and 1x192-bit data formats only. Figure 19. Continuous reading mode disabled, 1x256-bit data format 46/53 Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 Figure 20. Continuous reading mode enabled, 1x256-bit data format Recommended operating conditions Doc ID 022698 Rev 1 47/53 ...
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... Package mechanical data 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK trademark. 48/53 Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 Table 25. VFQFPN48 ( 1.0 mm.) package mechanical data Dim ddd (mm.) Min. Typ. 0.80 0.90 0.02 0.65 0.25 0.18 0.23 6.85 7.00 4.95 5.10 6.85 7.00 4.95 5.10 0.45 0.50 0.30 0.40 0.08 Doc ID 022698 Rev 1 Package mechanical data Max. 1.00 0.05 1.00 0.30 7.15 5.25 7.15 5.25 0.55 0.50 49/53 ...
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... Package mechanical data Figure 21. VFQFPN48 ( 1.0 mm.) package outline 50/53 Doc ID 022698 Rev 1 LED7708 ...
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... LED7708 Figure 22. Recommended PCB footprint 5.00 0.50 0.28 1.20 Doc ID 022698 Rev 1 Package mechanical data 8.60 AM11137v1 51/53 ...
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... Revision history 10 Revision history Table 26. Document revision history Date 07-May-2012 52/53 Revision 1 Initial release. Doc ID 022698 Rev 1 LED7708 Changes ...
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... LED7708 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...