NCP1612ADR2G ON Semiconductor, NCP1612ADR2G Datasheet

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NCP1612ADR2G

Manufacturer Part Number
NCP1612ADR2G
Description
Power Factor Correction ICs
Manufacturer
ON Semiconductor
Datasheet

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NCP1612
Enhanced, High‐Efficiency
Power Factor Controller
innovative Current Controlled Frequency Fold-back (CCFF) method.
In this mode, the circuit classically operates in Critical conduction
Mode (CrM) when the inductor current exceeds a programmable
value. When the current is below this preset level, the NCP1612
linearly decays the frequency down to about 20 kHz when the current
is null. CCFF maximizes the efficiency at both nominal and light load.
In particular, the stand-by losses are reduced to a minimum.
power factor even when the switching frequency is reduced. Housed in
a SO−10 package, the circuit also incorporates the features necessary
for robust and compact PFC stages, with few external components.
General Features
Safety Features
 Semiconductor Components Industries, LLC, 2013
April, 2013 − Rev. 2
The NCP1612 is designed to drive PFC boost stages based on an
Like in FCCrM controllers, an internal circuitry allows near-unity
Operation is Forced at Low Current Levels
Mode
(Dynamic Response Enhancer)
B Version: High V
Separate Pin for Fast Over-voltage Protection (FOVP)
and Bulk Under-voltage Detection (BUV)
Soft Over-voltage Protection
Brown-out Detection
Soft-start for Smooth Start-up Operation (A version)
Over Current Limitation
Disable Protection if the Feedback and FOVP/BUV
pins are not connected
Thermal Shutdown
Near-unity Power Factor
Critical Conduction Mode (CrM)
Current Controlled Frequency Fold-back (CCFF): Low Frequency
On-time Modulation to Maintain a Proper Current Shaping in CCFF
Skip Mode Near the Line Zero Crossing
Fast Line/Load Transient Compensation
Valley Turn On
High Drive Capability: −500 mA/+800 mA
V
Low Start-up Consumption
A Version: Low V
Line Range Detection
pfcOK Signal
This is a Pb-Free Device
CC
Range: from 9.5 V to 35 V
CC
CC
Start-up Level (10.5 V),
Start-up Level (17.0 V)
1
Typical Applications
Latched Off Capability
Low Duty-cycle Operation if the Bypass Diode is
shorted
Open Ground Pin Fault Monitoring
PC Power Supplies
All Off Line Appliances Requiring Power Factor
Correction
See detailed ordering and shipping information in the package
dimensions section on page 29 of this data sheet.
FOVP/BUV
Feedback
FFcontrol
V
V
1612x = Specific Device Code
A
L
Y
W
G
control
ORDERING INFORMATION
sense
MARKING DIAGRAM
PIN CONNECTIONS
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
CASE 751BQ
10
1
x = A or B
(Top View)
SOIC−10
1
1612x
ALYW
Publication Order Number:
G
pfcOK
V
DRV
GND
CS/ZCD
CC
NCP1612/D

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NCP1612ADR2G Summary of contents

Page 1

NCP1612 Enhanced, High‐Efficiency Power Factor Controller The NCP1612 is designed to drive PFC boost stages based on an innovative Current Controlled Frequency Fold-back (CCFF) method. In this mode, the circuit classically operates in Critical conduction Mode (CrM) when the inductor ...

Page 2

Table 1. MAXIMUM RATINGS Symbol Pin i(CS/ZCD CONTROL DRV 8 Power Dissipation and Thermal Characteristics P Maximum Power Dissipation @ qJA T Operating ...

Page 3

Table 2. TYPICAL ELECTRICAL CHARACTERISTICS (Conditions from −40C to +125C, unless otherwise specified Symbol START-UP AND SUPPLY CIRCUIT V Start-up Threshold, V CC(on) V Minimum Operating Voltage, V CC(off) V CC(HYST ...

Page 4

Table 2. TYPICAL ELECTRICAL CHARACTERISTICS (Conditions from −40C to +125C, unless otherwise specified Symbol CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS V Current Sense Voltage Reference CS(th) T Over-current Protection Leading Edge Blanking ...

Page 5

Table 2. TYPICAL ELECTRICAL CHARACTERISTICS (Conditions from −40C to +125C, unless otherwise specified Symbol FAST OVER VOLTAGE PROTECTION AND BULK UNDER-VOLTAGE PROTECTION (FAST OVP AND BUV) V BUV Threshold, V BUV R Ratio ...

Page 6

Table 3. DETAILED PIN DESCRIPTION Pin Number Name 1 FOVP/BUV V comparators. The circuit disables the driver higher than the reference for the soft OVP comparator (that monitors the feedback pin) so that pins 1 and 2 ...

Page 7

Figure 2. Block Diagram http://onsemi.com 7 ...

Page 8

T , JUNCTION TEMPERATURE (C) J Figure 3. Start-up Threshold vs. Temperature (A Version) CC(on) 10.00 9.75 9.50 9.25 9.00 8.75 8.50 8.25 8.00 ...

Page 9

T , JUNCTION TEMPERATURE (C) J Figure 9. FFcontrol Pin Current, V 1.4 V and V Maximum vs. Temperature CONTROL 22.5 20.5 18.5 16.5 14.5 ...

Page 10

T , JUNCTION TEMPERATURE (C) J Figure 15. DRV Source Resistance vs. Temperature −50 −30 − ...

Page 11

T , JUNCTION TEMPERATURE (C) J Figure 21. Error Amplifier Transconductance Gain vs. Temperature 0.5 0.4 0.3 0.2 0.1 0 −50 −30 − JUNCTION ...

Page 12

T , JUNCTION TEMPERATURE (C) J Figure 27. “Overstress” Protection Leading Edge Blanking vs. Temperature 850 800 750 700 650 −50 −30 − ...

Page 13

T , JUNCTION TEMPERATURE (C) J Figure 33. CS/ZCD Pin Bias Current @ V = 0.75 V vs. Temperature 960 920 880 840 ...

Page 14

T , JUNCTION TEMPERATURE (C) J Figure 39. Maximum On Time @ V 1.4 V vs. Temperature 100 −50 ...

Page 15

T , JUNCTION TEMPERATURE (C) J Figure 45. Ratio (fastOVP Threshold, V Rising) over V FOVP/BUV REF 290 270 250 230 210 190 170 150 ...

Page 16

T , JUNCTION TEMPERATURE (C) J Figure 51. Brown-out Threshold, V Falling vs. Temperature −50 −30 − JUNCTION TEMPERATURE ...

Page 17

T , JUNCTION TEMPERATURE (C) J Figure 57. Blanking Time for Line Range Detection vs. Temperature Introduction The NCP1612 is designed to optimize the efficiency of your PFC ...

Page 18

PFC stage extremely robust and reliable. In addition to the OVP protection, these methods of protection are provided: − Maximum Current Limit: the circuit senses the MOSFET current ...

Page 19

Top: CrM operation when the current information exceeds the preset level during the demagnetization phase Middle: the circuit re-starts at the next valley if the sum (ramp + current information) exceeds the preset level during the dead-time, while the drain-source ...

Page 20

Current Information Generation The “FFcontrol” pin sources a current that is representative of the input current. In practice multiplying the internal control signal (V internal signal that controls the on-time) by the sense voltage (pin 4) that is ...

Page 21

CCFF maximizes the efficiency at both nominal and light load. In particular, the stand−by losses are reduced to a minimum. Also, this method avoids that the system stalls between valleys. Instead, the circuit acts so that the PFC Figure 63. ...

Page 22

NCP1612 On-time Modulation Let’s analyze the ac line current absorbed by the PFC boost stage. The initial inductor current at the beginning of each switching cycle is always zero. The coil current ramps up when the MOSFET is on. The ...

Page 23

Hence, the maximum power that can be delivered by the PFC stage is in,rms P + in,avg max low line in,rms P + in,avg max ...

Page 24

The output of the error amplifier is brought to pin 3 for external loop compensation. Typically a type-2 network is applied between pin 3 and ground, to set the regulation bandwidth below about 20 Hz and to provide a decent ...

Page 25

OVP function (V = 105%  V out,sovp precedent section). This second protection offers some redundancy for a higher safety level. The FOVP threshold is set 2% higher than ...

Page 26

In both cases, the current can be large enough to trigger the ZCD comparator. An AND gate detects that this event occurs while the drive signal is high. In this ...

Page 27

The circuit also incorporates a comparator to a 7.5 V threshold so that the part latches off if the pfcOK pin voltage exceeds 7.5 V. This pin is to protect the part in presence of a major fault like a ...

Page 28

Thermal Shutdown (TSD) An internal thermal circuitry disables the circuit gate drive and keeps the power switch off when the junction temperature exceeds 150C. The output stage is then enabled once the temperature drops below about 100C (50C hysteresis). The ...

Page 29

... If such a fault is detected for 200 ms, the circuit stops operating. Table 4. ORDERING INFORMATION Device Circuit Version NCP1612ADR2G NCP1612A NCP1612BDR2G NCP1612B †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...

Page 30

... A1 SIDE VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’ ...

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