AT24C512BW-SH-T Atmel, AT24C512BW-SH-T Datasheet

IC EEPROM 512KBIT 1MHZ 8SOIC

AT24C512BW-SH-T

Manufacturer Part Number
AT24C512BW-SH-T
Description
IC EEPROM 512KBIT 1MHZ 8SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT24C512BW-SH-T

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
512K (64K x 8)
Speed
1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
Description
The AT24C512B provides 524,288 bits of serial electrically erasable and programma-
ble read only memory (EEPROM) organized as 65,536 words of 8 bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is
available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions.
Table 0-1.
Pin Name
A0–A2
SDA
SCL
WP
Low-voltage and Standard-voltage Operation
Internally Organized 65,536 x 8
Two-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (2.5V, 5.5V), 400 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
128-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
Lead-free/Halogen-free Devices
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2, and
8-lead Ultra Thin Small Array (SAP) Packages
Die Sales: Wafer Form, Waffle Pack and Bumped Die
– 1.8v (V
– 2.5v (V
– Endurance: 1,000,000 Write Cycles
– Data Retention: 40 Years
VCC
SDA
SCL
WP
8-ball dBGA2
Bottom View
8
7
6
5
CC
CC
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Pin Configurations
= 1.8V to 3.6V)
= 2.5V to 5.5V)
1
2
3
4
A0
A1
A2
GND
8-lead Ultra Thin SAP
VCC
SDA
SCL
WP
GND
Bottom View
8
7
6
5
A0
A1
A2
8-lead TSSOP
1
2
3
4
1
2
3
4
A0
A1
A2
GND
8
7
6
5
VCC
WP
SCL
SDA
GND
A0
A1
A2
GND
8-lead SOIC
A0
A1
A2
1
2
3
4
8-lead PDIP
1
2
3
4
8
7
6
5
8
7
6
5
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
with Three Device Address Inputs
Two-wire Serial
EEPROM
512K (65,536 x 8)
AT24C512B
Rev. 5297A–SEEPR–1/08

Related parts for AT24C512BW-SH-T

AT24C512BW-SH-T Summary of contents

Page 1

... Description The AT24C512B provides 524,288 bits of serial electrically erasable and programma- ble read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential ...

Page 2

Absolute Maximum Ratings* Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Figure 0-1. Block Diagram VCC GND ...

Page 3

... If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. ...

Page 4

... Memory Organization AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address. (1) Table 2-1. Pin Capacitance Applicable over recommended operating range from: T Symbol Test Condition C Input/Output Capacitance (SDA) I/O C Input Capacitance (A ...

Page 5

Table 2-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from T erwise noted). Test conditions are listed in Note 2. Symbol Parameter f Clock Frequency, SCL SCL t Clock Pulse Width Low LOW t Clock Pulse Width High ...

Page 6

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Data changes during SCL high periods will indicate ...

Page 7

Figure 3-2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O) SCL t SU.STA SDA IN SDA OUT Figure 3-3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) SCL SDA 8th BIT WORDn Note: 1. The write cycle ...

Page 8

Figure 3-4. Data Validity SDA SCL Figure 3-5. Start and Stop Definition SDA SCL Figure 3-6. Output Acknowledge SCL DATA IN DATA OUT AT24C512B 8 DATA STABLE DATA STABLE DATA CHANGE START 1 START STOP 8 9 ACKNOWLEDGE 5297A–SEEPR–1/08 ...

Page 9

... The data word address lower 7 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the follow- ing byte is placed at the beginning of the same page. If more than 128 data words are transmitted to the EEPROM, the data word address will “ ...

Page 10

... The address roll over during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the Read/Write select bit set to “1” is clocked in and acknowl- edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “ ...

Page 11

Figure 6-3. Page Write Figure 6-4. Current Address Read Figure 6-5. Random Read Figure 6-6. Sequential Read 5297A–SEEPR–1/08 AT24C512B 11 ...

Page 12

... AT24C512BN-SH-B (NiPdAu Lead Finish) (2) AT24C512BN-SH-T (NiPdAu Lead Finish) (1) AT24C512BN-SH25-B (NiPdAu Lead Finish) (2) AT24C512BN-SH25-T (NiPdAu Lead Finish) (1) AT24C512BW-SH-B (NiPdAu Lead Finish) (2) AT24C512BW-SH-T (NiPdAu Lead Finish) (1) AT24C512BW-SH25-B (NiPdAu Lead Finish) (2) AT24C512BW-SH25-T (NiPdAu Lead Finish) (1) AT24C512B-TH-B (NiPdAu Lead Finish) (2) AT24C512B-TH-T (NiPdAu Lead Finish) (1) AT24C512B-TH25-B ...

Page 13

Part marking scheme: 7.1 8-PDIP(1.8V) TOP MARK Seal Year |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 7.2 8-PDIP(2.5V) TOP MARK Seal Year |---|---|---|---|---|---|---|---| A T ...

Page 14

TOP MARK |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 7.4 8-SOIC(2.5V) TOP MARK |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| ...

Page 15

TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * |---|---|---|---|---| |---|---|---|---|---| BOTTOM MARK |---|---|---|---|---|---|---| |---|---|---|---|---|---|---| |---|---|---|---|---|---|---| <- Pin 1 Indicator 7.6 8-TSSOP(2.5V) ...

Page 16

Thin SAP (1.8V) TOP MARK Seal Year |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| Lot Number |---|---|---|---|---|---|---|---| * | Pin 1 Indicator (Dot) 7.8 8-Ultra Thin SAP (2.5V) TOP MARK Seal Year |---|---|---|---|---|---|---|---| ...

Page 17

... M = SEAL MONTH (USE ALPHA DESIGNATOR A- JANUARY B = FEBRUARY " " """"""" OCTOBER K = NOVEMBER L = DECEMBER TC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPOND WITH ATK TRACE CODE LOG BOOK) 5297A–SEEPR–1/08 2FBU YMTC |<-- Pin 1 This Corner 7: 2007 ...

Page 18

Package Information U2-1 - dBGA2 A1 BALL PAD CORNER e (e1) 5. Dimension 'b' is measured at the maximum solder ball diameter. This drawing is for general information only. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R ...

Page 19

PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the ...

Page 20

JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R ...

Page 21

EIAJ SOIC e e Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included recommended ...

Page 22

TSSOP Pin 1 indicator this corner N Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, ...

Page 23

UTSAP PIN 1 INDEX AREA D E 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R 5297A–SEEPR–1/08 A PIN COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.00 ...

Page 24

A1 BALL PAD CORNER e (e1) BOTTOM VIEW 5. Dimension 'b' is measured at the maximum solder ball diameter. This drawing is for general information only. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT24C512B ...

Page 25

Revision History Doc. Rev. 5297A 5297A–SEEPR–1/08 Date Comments AT24C512B product with date code 2008 work week 14 (814) or later supports 5Vcc operation 1/2008 Initial document release AT24C512B 25 ...

Page 26

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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