24LC512T-I/SM Microchip Technology, 24LC512T-I/SM Datasheet - Page 6

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24LC512T-I/SM

Manufacturer Part Number
24LC512T-I/SM
Description
IC EEPROM 512KBIT 400KHZ 8SOIC
Manufacturer
Microchip Technology
Datasheets

Specifications of 24LC512T-I/SM

Memory Size
512K (64K x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Memory Configuration
64K X 8
Ic Interface Type
I2C
Clock Frequency
400kHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
SOIJ
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
24LC512T-I/SM
24LC512T-I/SMTR

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24AA512/24LC512/24FC512
2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
The A0, A1 and A2 inputs are used by the 24XX512 for
multiple device operations. The logic levels on these
inputs are compared with the corresponding bits in the
slave address. The chip is selected if the compare is
true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable logic device,
the chip address pins must be driven to logic ‘0’ or logic
‘1’ before normal device operation can proceed.
2.2
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
DS21754M-page 6
Name
(NC)
SDA
(NC)
SCL
V
V
WP
A0
A1
A2
SS
CC
PIN DESCRIPTIONS
A0, A1 and A2 Chip Address
Inputs
Serial Data (SDA)
PDIP
1
2
3
4
5
6
7
8
CC
PIN FUNCTION TABLE
(typical 10 k for 100 kHz, 2 kfor
SOIC
1
2
3
4
5
6
7
8
SOIJ
1
2
3
4
5
6
7
8
CC
or V
TSSOP
SS
1
2
3
4
5
6
7
8
.
10, 11, 12
14-lead
TSSOP
3, 4, 5
13
14
1
2
6
7
8
9
2.3
This input is used to synchronize the data transfer from
and to the device.
2.4
This pin must be connected to either V
to V
write operations are inhibited but read operations are
not affected.
3.0
The 24XX512 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX512 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the
master device determines which mode is activated.
DFN
1
2
3
4
5
6
7
8
SS
, write operations are enabled. If tied to V
Serial Clock (SCL)
Write-Protect (WP)
FUNCTIONAL DESCRIPTION
CS
3
2
5
8
6
7
4
1
User Configured Chip Select
User Configured Chip Select
Not Connected
User Configured Chip Select
Ground
Serial Data
Serial Clock
Not Connected
Write-Protect Input
+1.7V to 5.5V (24AA512)
+2.5V to 5.5V (24LC512)
+1.7V to 5.5V (24FC512)
 2010 Microchip Technology Inc.
Function
SS
or V
CC
. If tied
CC
,

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