24LC512T-I/SM Microchip Technology, 24LC512T-I/SM Datasheet - Page 9

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24LC512T-I/SM

Manufacturer Part Number
24LC512T-I/SM
Description
IC EEPROM 512KBIT 400KHZ 8SOIC
Manufacturer
Microchip Technology
Datasheets

Specifications of 24LC512T-I/SM

Memory Size
512K (64K x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Memory Configuration
64K X 8
Ic Interface Type
I2C
Clock Frequency
400kHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
SOIJ
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
24LC512T-I/SM
24LC512T-I/SMTR

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5.0
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX512 this is set as ‘
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1 and A0). The Chip Select
bits allow the use of up to eight 24XX512 devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because all
A15…A0 are used, there are no upper address bits that
are “don’t care”. The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX512 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX512 will select a read or
write operation.
FIGURE 5-2:
 2010 Microchip Technology Inc.
1
Control
Code
DEVICE ADDRESSING
0
1
Control Byte
0
A
2
ADDRESS SEQUENCE BIT ASSIGNMENTS
Select
1010’
Chip
Bits
A
1
A
0 R/W
binary for read and write
1010’
code and appro-
15
A
24AA512/24LC512/24FC512
14
A
Address High Byte
13
A
12
A
11
A
10
A
FIGURE 5-1:
5.1
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 4 Mbit
by adding up to eight 24XX512 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A16; A1 as address bit A17; and A2
as address bit A18. It is not possible to sequentially
read across device boundaries.
Start Bit
A
9
S
A
8
Contiguous Addressing Across
Multiple Devices
1
Control Code
0
A
7
Slave Address
1
Address Low Byte
CONTROL BYTE FORMAT
0
Read/Write Bit
Chip Select
A2
Acknowledge Bit
Bits
A1
DS21754M-page 9
A0
R/W
A
0
ACK

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