BR24L02F-WE2 Rohm Semiconductor, BR24L02F-WE2 Datasheet - Page 2

IC EEPROM 2KBIT 400KHZ 8SOP

BR24L02F-WE2

Manufacturer Part Number
BR24L02F-WE2
Description
IC EEPROM 2KBIT 400KHZ 8SOP
Manufacturer
Rohm Semiconductor
Datasheets

Specifications of BR24L02F-WE2

Memory Size
2K (256 x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOP
Clock Frequency
400kHz
Supply Voltage Range
1.8V To 5.5V
Memory Case Style
SOP
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (18-Jun-2010)
Package /
RoHS Compliant
Organization
256 K x 8
Interface Type
I2C
Maximum Clock Frequency
0.1 MHz
Access Time
3500 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
BR24L02F-WE2TR

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* When using at Ta = 25°C or higher, 4.5mW (*1, *2), 3.0mW (*3), 3.3mW (*4)
SCL
SDA
3.1mW (*5,*6) to be reduced per 1°C
"HIGH" input voltage 1
"LOW" input voltage 1
"HIGH" input voltage 2
"LOW" input voltage 2
"HIGH" input voltage 3 *3
"HIGH" input voltage 3 *4
"LOW" input voltage 3 *2
"LOW" output voltage 1
"LOW" output voltage 2
Input leak current
Output leak current
Current consumption at
action
Standby current
temperature range
temperature range
Impressed voltage
Radiation resistance design is not made.
Terminal voltage
(Output)
SCL
SDA
(Input)
SCL
SDA
SDA
Permissible
Electrical characteristics
(Unless otherwise specified, Ta = -40 ~ +85°C, Vcc = 1.8 ~ 5.5V)
Absolute maximum ratings
Sync data input / output timing
Parameter
dissipation
Storage
Parameter
Action
FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is not changed. They are distinguished by action speeds. 100kHz
action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum action frequency,
so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action at high speed is not carried out,
therefore, at Vcc = 2.5V ~ 5.5V, 400kHz, namely, action is made in FASTMODE. (Action is made also in STANDARD-MODE) Vcc =
1.8V ~ 2.5V is only action in 100kHz STANDARD-MODE.
(n-th address)
Write data
Input read at the rise edge of SCL
Data output in sync with the fall of SCL
t
SU
: STA
t
HD :
t
D0
BUF
Symbol
Tstg
Topr
V
STA
Symbol
Pd
-
V
V
CC
V
V
V
V
V
V
V
I
I
I
I
CC1
CC2
I
OL1
OL2
LO
SB
IH1
IL1
IH2
IL2
IH3
IH3
IL3
LI
ACK
Fig.1-(a) Sync data input / output timing
0.7V
-0.3 *2
-0.3 *2
0.8V
0.9V
0.8V
Min.
-0.3
START BIT
t
HD
-1
-1
-
-
-
-
-
Fig.1-(b) Start - stop bit timing
CC
CC
CC
CC
: STA
Fig.1-(c) Write cycle timing
t
-0.3 ~ +6.5
-65 ~ +125
-40 ~ +85
-0.3 ~ V
R
450
450
300
330
310
310
*1
*2
*3
Limits
Typ.
Stop condition
Limits
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(SOP8)
(SOP-J8)
(SSOP-B8)
(TSSOP-B8)
(MSOP8)
(TSSOP-B8J)
t
BR24L16/L32-W : 1.7~5.5V
BR24L16/L32-W
BR24L16-W
SU
: DAT
V
V
CC
V
V
0.3V
CC
CC
0.2V
0.1V
2.0 *5
3.0 *6
Max.
CC
CC
(Ta=25˚C)
+1.0
+1.0 *2
+1.0 *2
0.4
0.2
0.5
2.0
1
1
+1.0
+1.0
CC
CC
CC
t
*1
*2
*3
*4
*5
*6
WR
Unit
mA
mA
µA
µA
µA
t
t
t
V
V
V
V
V
V
V
V
V
F
LOW
PD
t
SU
mW
Unit
˚C
˚C
: STO
V
V
2.5V≤V
2.5V≤V
1.8V≤V
1.8V≤V
1.7V≤V
1.7V≤V
1.7V≤V
I
I
V
V
V
Byte write, page write
V
Random read, current read, sequential
read
V
A0, A1, A2=GND, WP=GND
OL
OL
IN
OUT
CC
CC
CC
Start condition
=3.0mA, 2.5V≤V
=0.7mA, 1.7V≤V
=0V ~ V
=5.5V, f
=5.5V, f
=5.5V, SDA·SCL=V
=0V ~ V
t
*4
*5
*6
HIGH
CC
CC
CC
CC
CC
CC
CC
≤5.5V
≤5.5V
<2.5V
<2.5V
<1.8V
<1.8V
<1.8V
CC
BR24L32-W
BR24L01A/L02/L04/L08/L16-W
BR24L32/L64-W
SCL
SCL
CC
*1 BR24L16/L32-W : 1.7~5.5V
Power source
=400kHz, t
=400kHz
Parameter
Conditions
Input voltage
(SDA)
voltage
Recommended action conditions
CC
CC
t
DH
STOP BIT
≤5.5V, (SDA)
<2.5V, (SDA)
t
HD
CC
WR
,
: DAT
=5ms,
Symbol
V
V
*1
CC
IN
2/16
1.8 ~ 5.5
0 ~ V
Limits
SCL frequency
Data clock "HIGH" time
Data clock "LOW" time
SDA,SCL rise time
SDA,SCL fall time
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA,SCL terminal)
WP hold time
WP setup time
WP valid time
SCL
SDA
WP
SDA
SCL
WP
At write execution, in the area from the DO taken clock rise of the first DATA (1), to tWR, set WP =
"LOW".
By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = "HIGH" during tWR, write is forcibly ended, and data of address under access is not
guaranteed, therefore write it once again.
Action timing characteristics
(Unless otherwise specified, Ta=-40 ~ +85˚C, Vcc=1.8 ~ 5.5V)
CC
*1
D1
D1
DATA (1)
DATA (1)
Unit
V
V
t
Parameter
SU : WP
D0
D0
*2
*2
Number of data rewrite times
Data hold years
Shipment data all address FFh
ACK
ACK
Memory cell characteristics
Fig.1-(d) WP timing at write execution
Fig.1-(e) WP timing at write cancel
Parameter
t
HIGH : WP
tHIGH:WP
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:WP
tSU:WP
Symbol
tHIGH
tLOW
DATA (n)
fSCL
tBUF
tWR
tPD
tDH
DATA (n)
tR
tF
tl
Min.
100
0.6
1.2
0.6
0.6
0.1
0.1
0.6
1.2
0.1
1.0
0
0
2.5V
-
-
-
-
-
*2
*2
FAST-MODE
1,000,000
Typ.
Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min.
40
5.5V
ACK
ACK
(Ta = 25˚C, Vcc = 1.8 ~ 5.5V)
Max.
400
0.3
0.3
0.9
0.1
5
-
-
-
-
-
-
-
-
-
-
-
-
Stop condition
*1 BR24L16/L32-W : 1.7~5.5V
*2 Not 100% TESTED
STANDARD-MODE
Min.
250
4.0
4.7
4.0
4.7
0.2
0.2
4.7
4.7
0.1
1.0
Limits
*1 BR24L16/L32-W : 1.7~5.5V
*2 Not 100% tested.
1.8V
0
0
Typ.
-
-
-
-
-
-
-
t
WR
Vcc
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t
WR
5.5V
Max.
Max.
100
1.0
0.3
3.5
0.1
-
-
5
-
-
-
-
-
-
-
-
-
-
-
-
t
HD : WP
Times
Years
Unit
kHz
Unit
ms
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
ns
µs
µs
*1
*1

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